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Xiaofeng Yang

Orcid: 0000-0002-4150-2213

Affiliations:
  • Xi'an University of Post & Telecommunication, China


According to our database1, Xiaofeng Yang authored at least 9 papers between 2022 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Design and Verification of a High Performance Deserial Serial Peripheral Interface.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Yongnian Jiang
,
Mingxi Ren
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

Design of 18-25GHz On-chip Double-balanced Passive Mixer.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Pingyan Dong
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

Design of High Performance Dynamic DMA Based on Multidimensional Nesting Technology.
[BibTeX]
[DOI]
Xin Li
,
Xiaofeng Yang
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

Research on Spaceborne Memory Control Based on FPGA Configuration Refresh Technology.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Chuang Wu
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

Design and verification of SRAM controller based on FPGA.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Gulin Chen
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

2022
Bad Block Detection of Spaceborne NAND Flash Based on FPGA.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Jinjin Wang
,
Ancheng Liu
Proceedings of the 5th International Conference on Artificial Intelligence and Pattern Recognition, 2022

Design of Communication Controller Chip Based on FlexRay Bus.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Yaling Su
Proceedings of the 5th International Conference on Artificial Intelligence and Pattern Recognition, 2022

Design and Implementation of Miniaturized Flight Control Computer Based on FPGA+DSP.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Chaochao Qiu
Proceedings of the 5th International Conference on Artificial Intelligence and Pattern Recognition, 2022

High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM.
[BibTeX]
[DOI]
Xiaofeng Yang
,
Ancheng Liu
,
Jinjin Wang
Proceedings of the 5th International Conference on Artificial Intelligence and Pattern Recognition, 2022


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