Xiaofeng Yang
Orcid: 0000-0003-1400-7994Affiliations:
- University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Macau
According to our database1,
Xiaofeng Yang
authored at least 4 papers
between 2018 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
A 0.016mm<sup>2</sup> Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
2020
A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT.
IEEE Trans. Circuits Syst., 2020
2019
A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018