Xiaofei Ma

Orcid: 0000-0002-4481-428X

Affiliations:
  • University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Macau, China
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong


According to our database1, Xiaofei Ma authored at least 6 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control.
IEEE J. Solid State Circuits, June, 2024

D<sup>2</sup> Buck Converter With Delay-Insensitive Response and Adaptive On-Time Extension During Load Transient.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2022
A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020
A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS.
IEEE Trans. Circuits Syst., 2020

2018
A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


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