Xiaobing Shi
According to our database1,
Xiaobing Shi
authored at least 14 papers
between 2012 and 2024.
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Bibliography
2024
TRA-PS: Accountable data Pub/Sub service with fast and fine-grained controllable subscription.
J. Syst. Archit., 2024
2023
Dual-Path Information Fusion and Twin Attention-Driven Global Modeling for Solar Irradiance Prediction.
Sensors, September, 2023
Fault Diagnosis of Wind Turbine Generators Based on Stacking Integration Algorithm and Adaptive Threshold.
Sensors, July, 2023
An Efficient Resilient MPC Scheme via Constraint Tightening Against Cyberattacks: Application to Vehicle Cruise Control.
Proceedings of the 20th International Conference on Informatics in Control, 2023
2021
IEEE Netw., 2021
A Security Awareness and Protection System for 5G Smart Healthcare Based on Zero-Trust Architecture.
IEEE Internet Things J., 2021
2017
A generic embedded sequence generator for constrained-random validation with weighted distributions.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
2015
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
On-chip constrained random stimuli generation for post-silicon validation using compact masks.
Proceedings of the 2014 International Test Conference, 2014
An 8Gb/s 0.75mW/Gb/s injection-locked receiver with constant jitter tracking bandwidth and accurate quadrature clock generation in 40nm CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2012
A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012