Xiaobao Yu

According to our database1, Xiaobao Yu authored at least 13 papers between 1995 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Creative Class of "Micro Culture" Creative Industry.
Proceedings of the Advances in Creativity, Innovation, Entrepreneurship and Communication of Design, 2021

2019
Exploration and Thinking on the Cultural Communication of Guangdong Museum.
Proceedings of the Advances in Human Factors in Communication of Design, 2019

Research on the Historical Context of Guangzhou Time-Honored Catering Brands' Narration.
Proceedings of the Advances in Human Factors in Communication of Design, 2019

2016
A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

1995
Metrics Applicable to Software Design.
Ann. Softw. Eng., 1995


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