Xianlong Hong

Integr., 2009

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A single layer zero skew clock routing in X architecture.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2009

Integrated interlayer via planning and pin assignment for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Modern Floorplanning with Boundary Clustering Constraint.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Efficient power network analysis with complete inductive modeling.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Incremental power optimization for multiple supply voltage design.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Simultaneous buffer and interlayer via planning for 3D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Cell shifting aware of wirelength and overlap.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Diffusion-driven congestion reduction for substrate topological routing.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Buffer Planning for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Multi-objective Floorplanning Based on Fuzzy Logic.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Fuzzy Systems and Knowledge Discovery, 2009

An efficient decoupling capacitance optimization using piecewise polynomial models.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Fast placement for large-scale hierarchical FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A novel thermal optimization flow using incremental floorplanning for 3D ICs.

[BibT_eX]

[DOI]

Xin Li

Yuchun Ma

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Random Walk Guided Decap Embedding for Power/Ground Network Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fashion: A Fast and Accurate Solution to Global Routing Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.

[BibT_eX]

[DOI]

Integr., 2008

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem.

[BibT_eX]

[DOI]

Integr., 2008

Large scale P/G grid transient simulation using hierarchical relaxed approach.

[BibT_eX]

[DOI]

Integr., 2008

Efficient range pattern matching algorithm for process-hotspot detection.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Low Power Gated Clock Tree Driven Placement.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.

[BibT_eX]

[DOI]

Yanming Jia

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Application of optical proximity correction technology.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2008

Full-chip routing system for reducing Cu CMP & ECP variation.

[BibT_eX]

[DOI]

Yanming Jia

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.

[BibT_eX]

[DOI]

Haixia Yan

Qiang Zhou

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

DFM Based Detailed Routing Algorithm for ECP and CMP.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

Leakage power optimization for clock network using dual-Vth technology.

[BibT_eX]

[DOI]

Weixiang Shen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Gate planning during placement for gated clock network.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

A novel performance driven power gating based on distributed sleep transistor network.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Topological routing to maximize routability for package substrate.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Heuristic power/ground network and floorplan co-design method.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Vertical via design techniques for multi-layered P/G networks.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Wire density driven top-down global placement for CMP variation control.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Yield-Driven Gridless Router.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.

[BibT_eX]

[DOI]

Yaoguang Wei

Integr., 2007

An efficient quadratic placement based on search space traversing technology.

[BibT_eX]

[DOI]

Integr., 2007

Partitioning-based decoupling capacitor budgeting via sequence of linear programming.

[BibT_eX]

[DOI]

Integr., 2007

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Voltage Island Generation in Cell Based Dual-Vdd Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

An accurate and efficient probabilistic congestion estimation model in x architecture.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

CMP-aware Maze Routing Algorithm for Yield Enhancement.

[BibT_eX]

[DOI]

Hailong Yao

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Interconnect Power Optimization Based on Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Power Delivery Aware Floorplanning for Voltage Island Designs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Congestion Driven Buffer Planning for X-Architecture.

[BibT_eX]

[DOI]

Hongjie Bai

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Fast 3D-BSG Algorithm for 3D Packing Problem.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Effective Acceleration of Iterative Slack Distribution Process.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

New timing and routability driven placement algorithms for FPGA synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Physical aware clock skew rescheduling.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Dummy fill aware buffer insertion during routing.

[BibT_eX]

[DOI]

Yanming Jia

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Statistical model order reduction for interconnect circuits considering spatial correlations.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Logic and Layout Aware Voltage Island Generation for Low Power Design.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Legitimate Skew Clock Routing with Buffer Insertion.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Multilevel Routing With Redundant Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

VLSI Block Placement With Alignment Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Power/Ground Network Optimization Considering Decap Leakage Currents.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

Priority-Based Routing Resource Assignment Considering Crosstalk.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.

[BibT_eX]

[DOI]

Integr., 2006

Time-domain analysis methodology for large-scale RLC circuits and its applications.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2006

Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Clock Skew Scheduling Under Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

High accurate pattern based precondition method for extremely large power/ground grid analysis.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

A novel low-power physical design methodology for MTCMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Congestion-driven W-shape multilevel full-chip routing framework.

[BibT_eX]

[DOI]

Hailong Yao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On handling the fixed-outline constraints of floorplanning using less flexibility first principles.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Performance and power aware buffered tree construction.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High performance clock routing in X-architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Floorplanning for 2.5-D system integration using multi-layer-BSG structure.

[BibT_eX]

[DOI]

Shuyi Zheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Buffer planning based on block exchanging.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient process-hotspot detection using range pattern matching.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Efficient early stage resonance estimation techniques for C4 package.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Signal-path driven partition and placement for analog circuit.

[BibT_eX]

[DOI]

Di Long

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

DraXRouter: global routing in X-Architecture with dynamic resource assignment.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

DFM-aware Routing for Yield Enhancement.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Spanning graph-based nonrectilinear steiner tree algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Crosstalk-Aware Routing Resource Assignment.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Shielding Area Optimization Under the Solution of Interconnect Crosstalk.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Timing-Driven Global Routing with Efficient Buffer Insertion.

[BibT_eX]

[DOI]

Jingyu Xu

Tong Jing

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Navigating Register Placement for Low Power Clock Network Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Crosstalk and Congestion Driven Layer Assignment Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Reliable buffered clock tree routing algorithm with process variation tolerance.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2005

A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Efficient Simulation of Power/Ground Networks with Package and Vias.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A new approach based on LFF for optimization of dynamic hardware reconfigurations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models.

[BibT_eX]

[DOI]

Yiqian Zhang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Zero skew clock routing with tree topology construction using simulated annealing method.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Interconnect delay optimization via high level re-synthesis after floorplanning.

[BibT_eX]

[DOI]

Yunfeng Wang

Jinian Bian

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Performance constrained floorplanning based on partial clustering [IC layout].

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.

[BibT_eX]

[DOI]

Di Long

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fixed-outline floorplanning with constraints through instance augmentation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A global interconnect optimization algorithm under accurate delay model using solution space smoothing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Integrated routing resource assignment for RLC crosstalk minimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.

[BibT_eX]

[DOI]

Proceedings of the Advances in Natural Computation, First International Conference, 2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications, 2005

Improved multilevel routing with redundant via placement for yield and reliability.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An improved direct boundary element method for substrate coupling resistance extraction.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new algorithm for layout of dark field alternating phase shifting masks.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Fixed-outline floorplanning based on common subsequence.

[BibT_eX]

[DOI]

Rong Liu

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A New Buffer Planning Algorithm Based on Room Resizing.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, 2005

Navigating registers in placement for clock network minimization.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Partitioning-based approach to fast on-chip decap budgeting and minimization.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

An efficient algorithm to fixed-outline floorplanning based on instance augmentation.

[BibT_eX]

[DOI]

Rong Liu

Proceedings of the 9th International Conference on Computer-Aided Design and Computer Graphics, 2005

Analysis of buffered hybrid structured clock networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

LFF algorithm for heterogeneous FPGA floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

The polygonal contraction heuristic for rectilinear Steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An improved P-admissible floorplan representation based on Corner Block List.

[BibT_eX]

[DOI]

Renshen Wang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An-OARSMan: obstacle-avoiding routing tree construction with good length performance.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

VLSI on-chip power/ground network optimization considering decap leakage currents.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Relaxed hierarchical power/ground grid analysis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Stairway compaction using corner block list and its applications with rectilinear blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2004

Corner block list representation and its application to floorplan optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Area minimization of power distribution network using efficient nonlinear programming techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Leakage Current Estimation of CMOS Circuit with Stack Effect.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2004

Fast Evaluation of Bounded Slice-Line Grid.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2004

Corner block list representation and its application with boundary constraints.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2004

A buffer planning algorithm for chip-level floorplanning.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2004

An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Quick and effective buffered legitimate skew clock routing.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Shielding area optimization under the solution of interconnect crosstalk.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance and RLC crosstalk driven global routing.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk driven routing resource assignment.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Algorithm for yield driven correction of layout.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Layer assignment algorithm for RLC crosstalk minimization.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Partial random walk for large linear network analysis.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Module placement based on quadratic programming and rectangle packing using less flexibility first principle.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Efficient octilinear Steiner tree construction based on spanning graphs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Buffer allocation algorithm with consideration of routing congestion.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

SSTT: Efficient Local Search for GSI Global Routing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

FaSa: A Fast and Stable Quadratic Placement Algorithm.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

An efficient hierarchical timing-driven Steiner tree algorithm for global routing.

[BibT_eX]

[DOI]

Integr., 2003

A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

An integrated floorplanning with an efficient buffer planning algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining clustering and partitioning in quadratic placement.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Algorithms for analog VLSI 2D stack generation and block merging.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.

[BibT_eX]

[DOI]

Wenjian Yu

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction.

[BibT_eX]

[DOI]

Taotao Lu

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Congestion driven incremental placement algorithm for standard cell layout.

[BibT_eX]

[DOI]

Zhuoyuan Li

Weimin Wu

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A path-based timing-driven quadratic placement algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

An Optimum Placement Search Algorithm Based on Extended Corner Block List.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2002

A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2002

A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.

[BibT_eX]

[DOI]

Shuzhou Fang

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Floorplanning with abutment constraints based on corner block list.

[BibT_eX]

[DOI]

Integr., 2001

Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

VLSI floorplanning with boundary constraints based on corner block list.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

A new congestion-driven placement algorithm based on cell inflation.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

VLSI block placement using less flexibility first principles.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

MMP: a novel placement algorithm for combined macro block and standard cell layout design.

[BibT_eX]

[DOI]

Hong Yu

Proceedings of ASP-DAC 2000, 2000

Area routing oriented hierarchical corner stitching with partial bin.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Hierarchical computation of 3-D interconnect capacitance using direct boundary element method.

[BibT_eX]

[DOI]

Jiangchun Gu

Proceedings of ASP-DAC 2000, 2000

A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells.

[BibT_eX]

[DOI]

Xiaohai Wu

Changge Qiao

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A Timing-Driven Block Placer Based on Sequence Pair Model.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.

[BibT_eX]

[DOI]

Jinsong Hou

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A New Global Routing Algorithm Independent Of Net Ordering.

[BibT_eX]

[DOI]

Haiyun Bao

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

TIGER: an efficient timing-driven global router for gate array and standard cell layout design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

VEAP: Global optimization based efficient algorithm for VLSI placement.

[BibT_eX]

[DOI]

Tianming Kong