Xiangsheng Fang

According to our database, Xiangsheng Fang authored at least 8 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.

Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.

Tai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.

Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.

Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Yiming Ouyang, Honghui Deng

Microelectron. J., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.

Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen

IEICE Electron. Express, 2017

2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2005

A BIST Scheme Based on Selecting State Generation of Folding Counters.

Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005