Xiangjian Kong

According to our database, Xiangjian Kong authored at least 6 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 73-dB-SNDR 2nd-Order Noise-Shaping SAR With a Low-Noise Time-Domain Comparator.

Mingchao Jian, Jiwei Zheng, Xiangjian Kong, Bo Sun, Chunbing Guo

IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

RFIC Reuse Techniques to Enable Ultra-Low-Power IoT: A Tutorial.

Kai Xu, Xiangjian Kong, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement.

Xiangjian Kong, Kai Xu, Robert Bogdan Staszewski, Mingchao Jian, Chunbing Guo

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter.

Ding Qiu, Xiangjian Kong, Mingchao Jian, Jiwei Zheng, Chunbing Guo

Microelectron. J., December, 2023

A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch.

Xiangjian Kong, Ding Qiu, Mingchao Jian, Chunbing Guo, Kai Xu

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

A 12-bit SAR ADC with a reversible V_CM-based capacitor switching scheme.

Mingchao Jian, Jiwei Zheng, Xiangjian Kong, Meng Yuan, Chunhua Zhang, Chunbing Guo, Bo Sun

Microelectron. J., 2022