Xia Zhao

Orcid: 0000-0001-6479-9200

Affiliations:
  • Ghent University, Department of Electronics and Information Systems, Belgium
  • National University of Defense Technology, Changsha, China (former)


According to our database1, Xia Zhao authored at least 22 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Cluster-aware scheduling in multitasking GPUs.
Real Time Syst., March, 2024

AdCoalescer: An Adaptive Coalescer to Reduce the Inter-Module Traffic in MCM-GPUs.
Proceedings of the 53rd International Conference on Parallel Processing, 2024

2023
Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA.
IEEE Trans. Parallel Distributed Syst., November, 2023

RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs.
IEEE Comput. Archit. Lett., 2023

NUBA: Non-Uniform Bandwidth GPUs.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2020
Selective Replication in Memory-Side GPU Caches.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

HSM: A Hybrid Slowdown Model for Multitasking GPUs.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
HeteroCore GPU to Exploit TLP-Resource Diversity.
IEEE Trans. Parallel Distributed Syst., 2019

Application-aware NoC management in GPUs multitasking.
J. Supercomput., 2019

CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs.
IEEE Trans. Computers, 2019

Intra-Cluster Coalescing and Distributed-Block Scheduling to Reduce GPU NoC Pressure.
IEEE Trans. Computers, 2019

Adaptive memory-side last-level GPU caching.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Get Out of the Valley: Power-Efficient Address Mapping for GPUs.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Intra-Cluster Coalescing to Reduce GPU NoC Pressure.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Classification-Driven Search for Effective SM Partitioning in Multitasking GPUs.
Proceedings of the 32nd International Conference on Supercomputing, 2018

2017
LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs.
IEEE Comput. Archit. Lett., 2017

BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A low-cost conflict-free NoC for GPGPUs.
Proceedings of the 53rd Annual Design Automation Conference, 2016


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