Xi Li

Orcid: 0000-0003-0147-1368

Affiliations:

Chinese Academy of Sciences, State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Shanghai, China

According to our database¹, Xi Li authored at least 20 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Bibliography

2024

A Low-Cost Quadruple-Node-Upsets Resilient Latch Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., October, 2024

A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

High PSR external capacitor-less LDO with adaptive supply-ripple cancellation technique.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., August, 2024

2023

In-memory computing based on phase change memory for high energy efficiency.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., October, 2023

2022

Post-silicon nano-electronic device and its application in brain-inspired chips.

[BibT_eX]

[DOI]

Frontiers Neurorobotics, September, 2022

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory.

[BibT_eX]

[DOI]

Sensors, 2022

2021

An Ultra-Low Quiescent Current Resistor-Less Power on Reset Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A self-start circuit with asymmetric inductors reconfigurable technology for dual-output boost converter for energy harvesting.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

2018

A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Enhanced read performance for phase change memory using a reference column.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2015

Methods to speed up read operation in a 64 Mbit phase change memory chip.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A smart primary side current sensing strategy for single stage isolated PFC controller.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

2014

A smart method of optimizing the read/write current on PCM array.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A novel auxiliary-free zero inductor current detection scheme for step down non-isolated LED driver.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Xi Li

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