Xi Chen

Affiliations:

SpringSoft Inc., San Jose, CA, USA
Novas Software Inc., San Jose, CA, USA
University of California at Riverside, CA, USA (former)

According to our database¹, Xi Chen authored at least 20 papers between 2002 and 2011.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2011

A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2009

Runtime deadlock analysis for system level design.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

Yosinori Watanabe

Des. Autom. Embed. Syst., 2009

2007

Bridging RTL and gate: correlating different levels of abstraction for design debugging.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006

Verification Approach of Metropolis Design Framework for Embedded Systems.

[BibT_eX]

[DOI]

Xi Chen

Harry Hsieh

Felice Balarin

Int. J. Parallel Program., 2006

Runtime Deadlock Analysis of SystemC Designs.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Communication and co-simulation infrastructure for heterogeneous system integration.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Simulation based deadlock analysis for system level designs.

[BibT_eX]

[DOI]

Xi Chen

Abhijit Davare

Harry Hsieh

Alberto L. Sangiovanni-Vincentelli

Yosinori Watanabe

Proceedings of the 42nd Design Automation Conference, 2005

2004

Logic of constraints: a quantitative performance and functional constraint formalism.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Assertion Based Verification and Analysis of Network Processor Architectures.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2004

Assertion-based power/performance analysis of network processor architectures.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Utilizing Formal Assertions for System Design of Network Processors.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Shared memory multiprocessor architectures for software IP routers.

[BibT_eX]

[DOI]

Yan Luo

Laxmi Narayan Bhuyan

Xi Chen

IEEE Trans. Parallel Distributed Syst., 2003

Formal Verification for Embedded System Designs.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2003

Verifying LOC based functional and performance constraints.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Automatic trace analysis for logic of constraints.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Case Studies of Model Checking for Embedded System Designs.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Simulation Trace Verification for Quantitative Constraints.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software for SoC, 2003

2002

Formal verification of embedded system designs at multiple levels of abstraction.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Xi Chen

Timeline

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On csauthors.net:

Bibliography

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