X. Shawn Wang
Orcid: 0000-0001-5650-6236
According to our database1,
X. Shawn Wang
authored at least 9 papers
between 2012 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2019
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Int. J. Comput. Vis. Robotics, 2018
2017
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017
2016
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2014
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.
IEEE J. Solid State Circuits, 2014
2013
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012