Wu-Tung Cheng

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Volume diagnosis data mining.

[BibT_eX]

[DOI]

Yue Tian

Proceedings of the 22nd IEEE European Test Symposium, 2017

Scan Chain Diagnosis Based on Unsupervised Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Online slack-time binning for IO-registered die-to-die interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

A wide-range clock signal generation scheme for speed grading of a logic core.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Testing of small delay faults in a clock network.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection.

[BibT_eX]

[DOI]

Xijiang Lin

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Diagnosis and Layout Aware (DLA) Scan Chain Stitching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Diagnosing timing related cell internal defects for FinFET technology.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

A test-application-count based learning technique for test time reduction.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Identify problematic layout patterns through volume diagnosis.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Monitoring the delay of long interconnects via distributed TDC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.

[BibT_eX]

[DOI]

Wu Yang

Proceedings of the 20th IEEE European Test Symposium, 2015

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.

[BibT_eX]

[DOI]

Xijiang Lin

Janusz Rajski

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Diagnose Failures Caused by Multiple Locations at a Time.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Test Compression Improvement with EDT Channel Sharing in SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Oscillation-Based Prebond TSV Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Distributed dynamic partitioning based diagnosis of scan chain.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Improve speed path identification with suspect path expressions.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

At-speed BIST for interposer wires supporting on-the-spot diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Mid-bond Interposer Wire Test.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Scan-Based Speed-Path Debug for a Microprocessor.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

A unified method for parametric fault characterization of post-bond TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Improved volume diagnosis throughput using dynamic design partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Programmable Leakage Test and Binning for TSVs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

A Hybrid Flow for Memory Failure Bitmap Classification.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis.

[BibT_eX]

[DOI]

Feng-Ming Kuo

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Deterministic IDDQ diagnosis using a net activation based model.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On Using Design Partitioning to Reduce Diagnosis Memory Footprint.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

On Reducing Scan Shift Activity at RTL.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Test cycle power optimization for scan-based designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Case study of scan chain diagnosis and PFA on a low yield wafer.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

A scalable quantitative measure of IR-drop effects for scan pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Scan based speed-path debug for a microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Full-circuit SPICE simulation based validation of dynamic delay estimation.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Diagnosis of Multiple Physical Defects Using Logic Fault Models.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Improved weight assignment for logic switching activity during at-speed test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Emulating and diagnosing IR-drop by using dynamic SDF.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Speed-Path Debug Using At-Speed Scan Test Patterns.

[BibT_eX]

[DOI]

Kun-Han Tsai

Proceedings of the 14th IEEE European Test Symposium, 2009

Improving compressed test pattern generation for multiple scan chain failure diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

At-Speed Scan Test Method for the Timing Optimization and Calibration.

[BibT_eX]

[DOI]

Kun-Han Tsai

Proceedings of the Eighteentgh Asian Test Symposium, 2009

On Improving Diagnostic Test Generation for Scan Chain Failures.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Survey of Scan Chain Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Automatic Test Pattern Generation for Interconnect Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Reducing Scan Shift Power at RTL.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Detection and Diagnosis of Static Scan Cell Internal Defect.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Diagnose Multiple Stuck-at Scan Chain Faults.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

A Robust Automated Scan Pattern Mismatch Debugger.

[BibT_eX]

[DOI]

Kun-Han Tsai

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Hyperactive Faults Dictionary to Increase Diagnosis Throughput.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Enhancing Transition Fault Model for Delay Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Faster defect localization in nanometer technology based on defective cell diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Interconnect open defect diagnosis with minimal physical information.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Diagnose compound scan chain and system logic defects.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

A complete test set to diagnose scan chain failures.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Scan Diagnosis and Its Successful Industrial Applications.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Programmable Scan-Based Logic Built-In Self Test.

[BibT_eX]

[DOI]

Liyang Lai

Thomas Rinderknecht

Proceedings of the 16th Asian Test Symposium, 2007

A RTL Testability Analyzer Based on Logical Virtual Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Fault Dictionary Based Scan Chain Failure Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

On Methods to Improve Location Based Logic Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

X-Press Compactor for 1000x Reduction of Test Data.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Diagnosis with Limited Failure Information.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Signature Based Diagnosis for Logic BIST.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Interconnect Open Defect Diagnosis with Physical Information.

[BibT_eX]

[DOI]

Wei Zou

Proceedings of the 15th Asian Test Symposium, 2006

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Full-speed field programmable memory BIST supporting multi-level looping.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

X-filter: filtering unknowns from compacted test responses.

[BibT_eX]

[DOI]

Manish Sharma

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Compression mode diagnosis enables high volume monitoring diagnosis flow.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Compressed pattern diagnosis for scan chain failures.

[BibT_eX]

[DOI]

Janusz Rajski

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Full-speed field-programmable memory BIST architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Hardware Ef.cient LBISTWith Complementary Weights.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Bridge Defect Diagnosis with Physical Information.

[BibT_eX]

[DOI]

Wei Zou

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Achieving High Test Quality with Reduced Pin Count Testing.

[BibT_eX]

[DOI]

Jay Jahangiri

Nilanjan Mukherjee

Subramanian Mahadevan

Ron Press

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Using fault model relaxation to diagnose real scan chain defects.

[BibT_eX]

[DOI]

Greg Crowell

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Logic BIST Using Constrained Scan Cells.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Memory BIST Using ESP.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Logic BIST with Scan Chain Segmentation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Compactor Independent Direct Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

BIST for Deep Submicron ASIC Memories with High Performance Application.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Silicon Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Using embedded infrastructure IP for SOC post-silicon verification.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Testing Delay Faults in Embedded CAMs.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Synthesis of Scan Chains for Netlist Descriptions at RT-Level.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Core - Clustering Based SOC Test Scheduling Optimization.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

On RTL scan design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Effect of RTL coding style on testability.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

High time for high level ATPG.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1996

A Universal Technique for Accelerating Simulation of Scan Test Patterns.

[BibT_eX]

[DOI]

Bejoy G. Oomman

John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1992

PROOFS: a fast, memory-efficient sequential circuit fault simulator.

[BibT_eX]

[DOI]

Thomas M. Niermann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Optimal diagnostic methods for wiring interconnects.

[BibT_eX]

[DOI]

James L. Lewandowski

Eleanor Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1990

Differential fault simulation for sequential circuits.

[BibT_eX]

[DOI]

Meng-Lin Yu

J. Electron. Test., 1990

Diagnosis for wiring interconnects.

[BibT_eX]

[DOI]

James L. Lewandowski

Eleanor Wu

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

PROOFS: a super fast fault simulator for sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

1989

Gentest: An Automatic Test-Generation System for Sequential Circuits.

[BibT_eX]

[DOI]

Tapan J. Chakraborty

Computer, 1989

Differential Fault Simulation - a Fast Method Using Minimal Memory.

[BibT_eX]

[DOI]

Meng-Lin Yu

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

The BACK algorithm for sequential test generation.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Split Circuit Model for Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1987

1985

Testing and Error Detection in Iterative Logic Arrays

[BibT_eX]

[DOI]

PhD thesis, 1985

Multiple-Fault Detection in Iterative Logic Arrays.

[BibT_eX]