Wooseok Byun

Orcid: 0000-0002-2720-3102

According to our database1, Wooseok Byun authored at least 9 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2022
Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End.
IEEE Trans. Biomed. Circuits Syst., 2020

2019
High-Speed Visual Target Identification for Low-Cost Wearable Brain-Computer Interfaces.
IEEE Access, 2019

A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2015
Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2015


  Loading...