Woongki Baek

Orcid: 0000-0002-1877-7307

According to our database1, Woongki Baek authored at least 47 papers between 2005 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Activation Sequence Caching: High-Throughput and Memory-Efficient Generative Inference with a Single GPU.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023
COSMOS: Coordinated Management of Cores, Memory, and Compressed Memory Swap for QoS-Aware and Efficient Workload Consolidation for Memory-Intensive Applications.
IEEE Access, 2023

MARF: A Memory-Aware CLFLUSH-Based Intra- and Inter-CPU Side-Channel Attack.
Proceedings of the Computer Security - ESORICS 2023, 2023

2022
SDRP: Safe, Efficient, and SLO-Aware Workload Consolidation Through Secure and Dynamic Resource Partitioning.
IEEE Trans. Serv. Comput., 2022

DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Holistic VM Placement for Distributed Parallel Applications in Heterogeneous Clusters.
IEEE Trans. Serv. Comput., 2021

Design and Implementation of a Criticality- and Heterogeneity-Aware Runtime System for Task-Parallel Applications.
IEEE Trans. Parallel Distributed Syst., 2021

PALM: Progress- and Locality-Aware Adaptive Task Migration for Efficient Thread Packing.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

HERTI: A Reinforcement Learning-Augmented System for Efficient Real-Time Inference on Heterogeneous Embedded Systems.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Hotness- and Lifetime-Aware Data Placement and Migration for High-Performance Deep Learning on Heterogeneous Memory Systems.
IEEE Trans. Computers, 2020

2019
Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache Management.
IEEE Trans. Parallel Distributed Syst., 2019

Analyzing and optimizing the performance and energy efficiency of transactional scientific applications on large-scale NUMA systems with HTM support.
J. Parallel Distributed Comput., 2019

CoPart: Coordinated Partitioning of Last-Level Cache and Memory Bandwidth for Fairness-Aware Workload Consolidation on Commodity Servers.
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

POSTER: The Performance Impact of Thread Packing on Synchronization-Intensive Applications.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

MOSAIC: Heterogeneity-, Communication-, and Constraint-Aware Model Slicing and Execution for Accurate and Efficient Inference.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Quantifying the Performance and Energy-Efficiency Impact of Hardware Transactional Memory on Scientific Applications on Large-Scale NUMA Systems.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

CEML: a Coordinated Runtime System for Efficient Machine Learning on Heterogeneous Computing Systems.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018

RPPC: A Holistic Runtime System for Maximizing Performance Under Power Capping.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

Secure and Dynamic Core and Cache Partitioning for Safe and Efficient Server Consolidation.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

Hypart: a hybrid technique for practical memory bandwidth partitioning on commodity servers.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems.
Proceedings of the International Conference on Supercomputing, 2017

Machine-Learning Based Performance Estimation for Distributed Parallel Applications in Virtualized Heterogeneous Clusters.
Proceedings of the 37th IEEE International Conference on Distributed Computing Systems, 2017

CHRT: A criticality- and heterogeneity-aware runtime system for task-parallel applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Failure-Atomic Slotted Paging for Persistent Memory.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Quantifying the performance and energy efficiency of advanced cache indexing for GPGPU computing.
Microprocess. Microsystems, 2016

HAPT: hardware-accelerated persistent transactions.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Quantifying the performance impact of large pages on in-memory big-data workloads.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

RCHC: A Holistic Runtime System for Concurrent Heterogeneous Computing.
Proceedings of the 45th International Conference on Parallel Processing, 2016

IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

HAP: A Heterogeneity-Conscious Runtime System for Adaptive Pipeline Parallelism.
Proceedings of the Euro-Par 2016: Parallel Processing, 2016

RMC: an integrated runtime system for adaptive many-core computing.
Proceedings of the 2016 International Conference on Embedded Software, 2016

NVWAL: Exploiting NVRAM in Write-Ahead Logging.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
On the Feasibility of Advanced Cache Indexing for High-Performance and Energy-Efficient GPGPU Computing.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

2010
Implementing and evaluating nested parallel transactions in software transactional memory.
Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

Green: a framework for supporting energy-conscious programming using controlled approximation.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Making nested parallel transactions practical using lightweight hardware support.
Proceedings of the 24th International Conference on Supercomputing, 2010

Implementing and Evaluating a Model Checker for Transactional Memory Systems.
Proceedings of the 15th IEEE International Conference on Engineering of Complex Computer Systems, 2010

2009
Fast memory snapshot for concurrent programmingwithout synchronization.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Improving software concurrency with hardware-assisted memory snapshot.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Ased: availability, security, and debugging support usingtransactional memory.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

2007
A Measurement-Based Automatic Energy Optimization Technique for Embedded Applications.
J. Low Power Electron., 2007

Towards soft optimization techniques for parallel cognitive applications.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

A Scalable, Non-blocking Approach to Transactional Memory.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

The OpenTM Transactional Application Programming Interface.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2005
Load-store reordering for low-power multimedia data transfers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


  Loading...