Woohyun Chung

Orcid: 0000-0002-1541-0745

According to our database1, Woohyun Chung authored at least 9 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Evaluation of Random Errors for Vector Network Analyzers Based on a Residual Model.
IEEE Trans. Instrum. Meas., 2024

Design of a Waveguide Calibration Kit Consisting of Offset Shorts for Low Measurement Uncertainty.
IEEE Access, 2024

2019
Integrated Latch Placement and Cloning for Timing Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

2017
Lithography Defect Probability and Its Application to Physical Design Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Placement optimization for MP-DSAL compliant layout.
Proceedings of the International Conference on IC Design and Technology, 2016

Redundant via insertion in directed self-assembly lithography.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Redundant via insertion for multiple-patterning directed-self-assembly lithography.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Identifying redundant inter-cell margins and its application to reducing routing congestion.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015


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