Woo-Young Choi
Orcid: 0000-0002-6175-5533
According to our database1,
Woo-Young Choi
authored at least 110 papers
between 1989 and 2024.
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Bibliography
2024
Overshoot-Suppressed Memristor Array with AlN Oxygen Barrier for Low-Power Operation in the Intelligent Neuromorphic Systems.
Adv. Intell. Syst., August, 2024
Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks.
Adv. Intell. Syst., January, 2024
Resting-potential-adjustable soft-reset integrate-and-fire neuron model for highly reliable and energy-efficient hardware-based spiking neural networks.
Neurocomputing, 2024
StrikeNet: Deep Convolutional LSTM-Based Road Lane Reconstruction With Spatiotemporal Inference for Lane Keeping Control.
IEEE Access, 2024
IEEE Access, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Logic-Compatible Charge-Trapping Tunnel Field Effect Transistors for Low-Power, High-Accuracy, and Large-Scale Neuromorphic Systems.
Adv. Intell. Syst., November, 2023
In-Core Neutron Detection System Using a Dual-Mode Self-Reset Preamplifier With the Micro-Pocket Fission Detector.
IEEE Trans. Instrum. Meas., 2023
Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors.
IEEE Access, 2023
IEEE Access, 2023
IEEE Access, 2023
Doping-Optimized Back-illuminated Single-Photon Avalanche Diode in Stacked 40 nm CIS Technology Achieving 60% PDP at 905 nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
IEEE Trans. Intell. Transp. Syst., 2022
IEEE Trans. Ind. Informatics, 2022
Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
IEEE Trans. Ind. Informatics, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Data-Driven Object Vehicle Estimation by Radar Accuracy Modeling with Weighted Interpolation.
Sensors, 2021
IEEE Access, 2021
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
SAFE-STOP System: Tactical Intention Awareness Based Emergency Collision Avoidance for Malicious Cut-in of Surrounding Vehicle.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021
Digital Controller Implementation of Grid-Tied Zeta Inverter Using 16-bits Microcontroller.
Proceedings of the 18th International SoC Design Conference, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Int. J. Syst. Assur. Eng. Manag., 2020
Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs).
IEEE Access, 2020
Dynamic Slingshot Operation for Low-Operation- Voltage Nanoelectromechanical (NEM) Memory Switches.
IEEE Access, 2020
Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State.
IEEE Access, 2020
Proceedings of the 59th Annual Conference of the Society of Instrument and Control Engineers of Japan, 2020
A Fully Integrated 25 Gb/s Si Ring Modulator Transmitter with a Temperature Controller.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Local Path Planning Using Artificial Potential Field for Waypoint Tracking with Collision Avoidance.
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020
Proceedings of the International SoC Design Conference, 2020
Effective Software Scheme of the Space Vector Modulation Using One-Chip Micro-Controller.
Proceedings of the International SoC Design Conference, 2020
An Accurate and Computationally Efficient Large-signal SPICE Model for Depletion-type Silicon Ring Modulators Including Temperature Dependence.
Proceedings of the European Conference on Optical Communications, 2020
2019
Continuously Variable Stiffness Mechanism Using Nonuniform Patterns on Coaxial Tubes for Continuum Microsurgical Robot.
IEEE Trans. Robotics, 2019
A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Autonomous Lane Keeping Control System Based on Road Lane Model Using Deep Convolutional Neural Networks.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019
2018
IEEE Trans. Ind. Electron., 2018
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
Proceedings of the 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2018
Proceedings of the 2018 Annual American Control Conference, 2018
2017
Proceedings of the 11th Asian Control Conference, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Robotics Autom. Mag., 2016
Development of a Multi-functional Soft Robot (SNUMAX) and Performance in RoboSoft Grand Challenge.
Frontiers Robotics AI, 2016
Development of soft continuum manipulator with pneumatic and tendon driven actuations.
Proceedings of the 13th International Conference on Ubiquitous Robots and Ambient Intelligence, 2016
A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal-oxide semiconductor technology.
IET Circuits Devices Syst., 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEICE Trans. Electron., 2013
Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory.
IEICE Trans. Electron., 2013
A 10-Gb/s low-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram.
IEICE Electron. Express, 2013
2012
A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Fully integrated serial-link receiver with optical interface for long-haul display interconnects.
IET Circuits Devices Syst., 2012
Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs).
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology.
Proceedings of the International SoC Design Conference, 2012
Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012
60-GHz voltage-controlled oscillator and frequency divider in 0.25-µm SiGe BiCMOS technology.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Single-Stage Quasi-Resonant Flyback Converter for a Cost-Effective PDP Sustain Power Module.
IEEE Trans. Ind. Electron., 2011
IEICE Trans. Electron., 2011
A bandwidth adjustable integrated optical receiver with an on-chip silicon avalanche photodetector.
IEICE Electron. Express, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology.
Proceedings of the International SoC Design Conference, 2011
Supply noise insensitive ring VCO with on-chip adaptive bias-current and voltage-swing control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A New Network Synchronizer Using Phase Adjustment and Feedforward Filtering Based on Low-Cost Crystal Oscillators.
IEEE Trans. Instrum. Meas., 2010
IEICE Trans. Electron., 2010
IEICE Electron. Express, 2010
IEICE Electron. Express, 2010
IEICE Electron. Express, 2010
A 4.8-Gb/s mixed-mode CMOS QPSK demodulator for 60-GHz wireless personal area networks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
10Gbps injection-locked CDR with a simple bit transition detector in 0.18µm CMOS technology.
IEICE Electron. Express, 2009
2008
IEEE Trans. Ind. Electron., 2008
Cost-Effective Boost Converter With Reverse-Recovery Reduction and Power Factor Correction.
IEEE Trans. Ind. Electron., 2008
IEEE J. Solid State Circuits, 2008
J. Inform. and Commun. Convergence Engineering, 2008
A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator.
IEICE Trans. Commun., 2008
2007
IEEE Trans. Ind. Electron., 2007
Bridgeless Boost Rectifier With Low Conduction Losses and Reduced Diode Reverse-Recovery Problems.
IEEE Trans. Ind. Electron., 2007
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- μħbox m CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution.
IEICE Trans. Electron., 2007
Rapid generation of the piping model having the relationship with a hull structure in shipbuilding.
Adv. Eng. Softw., 2007
2006
A 0.18 µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link.
IEICE Trans. Electron., 2006
1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Quantitative Analysis of White Matter on DTI Images of Patients with Tinnitus: Preliminary Report.
Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006
2003
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2001
1998
Eight-point discrete Hartley transform as an edge operator and its interpretation in the frequency domain.
Pattern Recognit. Lett., 1998
1995
Adv. Robotics, 1995
1994
1992
Pattern Recognit. Lett., 1992
J. Circuits Syst. Comput., 1992
1990
IEEE Trans. Pattern Anal. Mach. Intell., 1990
1989
Comput. Vis. Graph. Image Process., 1989