Woo-Chan Park

Orcid: 0000-0002-9249-2887

According to our database1, Woo-Chan Park authored at least 57 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Efficient Haze Removal from a Single Image Using a DCP-Based Lightweight U-Net Neural Network Model.
Sensors, June, 2024

2023
An Implementation of Inverse Cosine Hardware for Sound Rendering Applications.
Sensors, August, 2023

Multi-Threaded Sound Propagation Algorithm to Improve Performance on Mobile Devices.
Sensors, January, 2023

An Architecture and Implementation of Real-Time Sound Propagation Hardware for Mobile Devices.
Proceedings of the SIGGRAPH Asia 2023 Conference Papers, 2023

2022
Effective Algorithm to Control Depth Level for Performance Improvement of Sound Tracing.
J. Web Eng., 2022

2021
Lossless Compression Algorithm and Architecture for Reduced Memory Bandwidth Requirement with Improved Prediction Based on the Multiple DPCM Golomb-Rice Algorithm.
J. Web Eng., 2021

An Implementation of Multi-Chip Architecture for Real-Time Ray Tracing Based on Parallel Frame Rendering.
IEEE Access, 2021

An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder.
IEEE Access, 2021

2020
A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers.
IEEE Access, 2020

Load Balancing Algorithm for Real-Time Ray Tracing of Dynamic Scenes.
IEEE Access, 2020

2019
A Practically Applicable Performance Prediction Model Based on Capabilities of Texture Mapping Units for Mobile GPUs.
IEEE Access, 2019

An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images.
IEEE Access, 2019

2018
Real-time 3D Audio Downmixing System based on Sound Rendering for the Immersive Sound of Mobile Virtual Reality Applications.
KSII Trans. Internet Inf. Syst., 2018

A Novel Performance Prediction Model for Mobile GPUs.
IEEE Access, 2018

2017
An Effective Viewport Resolution Scaling Technique to Reduce the Power Consumption in Mobile GPUs.
KSII Trans. Internet Inf. Syst., 2017

Real-time sound propagation hardware accelerator for immersive virtual reality 3D audio.
Proceedings of the 21st ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games, 2017

2016
Geometry transition method to improve ray-tracing precision.
Multim. Tools Appl., 2016

2015
HART: A Hybrid Architecture for Ray Tracing Animated Scenes.
IEEE Trans. Vis. Comput. Graph., 2015

2014
RayCore: A Ray-Tracing Hardware Architecture for Mobile Devices.
ACM Trans. Graph., 2014

Effective traversal algorithms and hardware architecture for pyramidal inverse displacement mapping.
Comput. Graph., 2014

RayChip®: Real-time ray-tracing chip for embedded applications.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013
A pixel pipeline architecture with selective z-test scheme for 3D graphics processors.
Microprocess. Microsystems, 2013

gkDtree: A group-based parallel update kd-tree for interactive ray tracing.
J. Syst. Archit., 2013

Ray-Box Culling for Tree Structures.
J. Inf. Sci. Eng., 2013

Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors.
IEICE Trans. Inf. Syst., 2013

Node pre-fetching architecture for real-time ray tracing.
IEICE Electron. Express, 2013

2012
Erratum: Efficient ray sorting for the tracing of incoherent rays [IEICE Electronics Express Vol.9 (2012), No 9 pp 849-854].
IEICE Electron. Express, 2012

Efficient ray sorting for the tracing of incoherent rays.
IEICE Electron. Express, 2012

2011
T&I engine: traversal and intersection engine for hardware accelerated ray tracing.
ACM Trans. Graph., 2011

A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC.
IEEE Trans. Circuits Syst. Video Technol., 2011

An effective depth data memory system using an escape count buffer for 3D rendering processors.
IEICE Electron. Express, 2011

The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing.
IEICE Electron. Express, 2011

An effective rasterization architecture for mobile vector graphics processors.
IEICE Electron. Express, 2011

2010
The design of compressed memory system for depth data in 3D rendering processors.
IEICE Electron. Express, 2010

A high performance network-on-chip scheme using lossless data compression.
IEICE Electron. Express, 2010

2008
An Effective Load Balancing Scheme for 3D Texture-Based Sort-Last Parallel Volume Rendering on GPU Clusters.
IEICE Trans. Inf. Syst., 2008

2007
A consistency-free memory architecture for sort-last parallel rendering processors.
J. Syst. Archit., 2007

An Effective Bump Mapping Hardware Architecture Using Polar Coordinate System.
J. Inf. Sci. Eng., 2007

Simulation and development environment for mobile 3D graphics architectures.
IET Comput. Digit. Tech., 2007

2006
An Effective Visibility Culling Method Based on Cache Block.
IEEE Trans. Computers, 2006

A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering.
Proceedings of the Architecture of Computing Systems, 2006

2005
A pixel cache architecture with selective placement scheme based on z-test result.
Microprocess. Microsystems, 2005

A Simple and Efficient Triangle Strip Filtering Algorithm.
J. Inf. Sci. Eng., 2005

2004
A Cost-Effective Pipelined Divider with a Small Lookup Table.
IEEE Trans. Computers, 2004

A Rendering-Efficient Progressive Transmission of 3D Meshes.
IEICE Trans. Inf. Syst., 2004

A Bandwidth Reduction Scheme for 3D Texture-Based Volume Rendering on Commodity Graphics Hardware.
Proceedings of the Computational Science and Its Applications, 2004

A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

Order Independent Transparency for Image Composition Parallel Rendering Machines.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

A Cost-Effective Supersampling for Full Scene AntiAliasing.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
IEEE Trans. Computers, 2003

An effective out-of-order execution control scheme for an embedded floating point coprocessor.
Microprocess. Microsystems, 2003

2002
Design of a Single Pass Rendering Pipeline for Occlusion Culling.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

A Pipelined Tiling-Traversal Unit for High Performance 3D Rendering Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

A New Bandwidth Reduction Method for Distributed Rendering Systems.
Proceedings of the EurAsia-ICT 2002: Information and Communication Technology, 2002

A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

1999
A floating point multiplier performing IEEE rounding and addition in parallel.
J. Syst. Archit., 1999


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