Wonseok Choi
Affiliations:- Samsung Electronics Inc., DRAM Design Team, Hwaseong, South Korea
- Korea University, School of Electrical Engineering, Seoul, South Korea (former)
According to our database1,
Wonseok Choi
authored at least 4 papers
between 2017 and 2021.
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Bibliography
2021
Exploiting Retraining-Based Mixed-Precision Quantization for Low-Cost DNN Accelerator Design.
IEEE Trans. Neural Networks Learn. Syst., 2021
2019
Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2017
An efficient convolutional neural networks design with heterogeneous SRAM cell sizing.
Proceedings of the International SoC Design Conference, 2017