Won-Chang Jung
According to our database1,
Won-Chang Jung
authored at least 2 papers
between 2016 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
2016
2017
0
1
2
1
1
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On csauthors.net:
Bibliography
2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017
2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016