Wolfgang Roesner

Orcid: 0009-0004-5483-3371

According to our database1, Wolfgang Roesner authored at least 12 papers between 1985 and 2024.

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Bibliography

2024
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs.
IEEE Des. Test, June, 2024

2019
Verification at RTL Using Separation of Design Concerns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2015
Designer-level verification: an industrial experience story.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Post-Silicon Validation of the IBM POWER8 Processor.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2009
Functional verification of the IBM System z10 processor chipset.
IBM J. Res. Dev., 2009

2008
ESL hand-off: fact or EDA fiction?
Proceedings of the 45th Design Automation Conference, 2008

2004
Configurable system simulation model build comprising packaging design data.
IBM J. Res. Dev., 2004

2003
What Is beyond the RTL Horizon for Microprocessor and System Design?
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM J. Res. Dev., 2002

2000
EDA in IBM: past, present, and future.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1988
The logic design language and verification environment for the VLSI-/370.
Microprocess. Microprogramming, 1988

1985
SESPATH: An ER Manipulation Language.
Proceedings of the Entity-Relationship Approach: The Use of ER Concept in Knowledge Representation, 1985


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