Wolfgang Roesner

According to our database, Wolfgang Roesner authored at least 12 papers between 1985 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs.

Arun Joseph, Pretty Mariam Jacob, Matthias Klein, Wolfgang Roesner

IEEE Des. Test, June, 2024

2019

Verification at RTL Using Separation of Design Concerns.

Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2015

Designer-level verification: an industrial experience story.

Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Post-Silicon Validation of the IBM POWER8 Processor.

Amir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2009

Functional verification of the IBM System z10 processor chipset.

Christopher A. Krygowski, Dean G. Bair, Rebecca M. Gott, M. H. Decker, A. V. Giri, Christian Habermann, Matthias Heizmann, Stefan Letz, William J. Lewis, Steven M. Licker, H. Mallar, Edward C. McCain, Wolfgang Roesner, N. Siddique, A. E. Seigler, Brian W. Thompto, K. Weber, Ralf Winkelmann

IBM J. Res. Dev., 2009

2008

ESL hand-off: fact or EDA fiction?

Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini

Proceedings of the 45th Design Automation Conference, 2008

2004

Configurable system simulation model build comprising packaging design data.

Hans-Werner Anderson, Hans Kriese, Wolfgang Roesner, Klaus-Dieter Schubert

IBM J. Res. Dev., 2004

2003

What Is beyond the RTL Horizon for Microprocessor and System Design?

Wolfgang Roesner

Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.

John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile

IBM J. Res. Dev., 2002

2000

EDA in IBM: past, present, and future.

John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1988

The logic design language and verification environment for the VLSI-/370.

Wolfgang Roesner

Microprocess. Microprogramming, 1988

1985

SESPATH: An ER Manipulation Language.

Wolfgang Roesner

Proceedings of the Entity-Relationship Approach: The Use of ER Concept in Knowledge Representation, 1985