Wolfgang Puffitsch

Orcid: 0009-0004-9363-4519

Affiliations:
  • Technical University of Denmark


According to our database1, Wolfgang Puffitsch authored at least 36 papers between 2004 and 2018.

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Bibliography

2018
Patmos: a time-predictable microprocessor.
Real Time Syst., 2018

2017
Hardware locks for a real-time Java chip multiprocessor.
Concurr. Comput. Pract. Exp., 2017

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy.
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

2016
TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Time-Predictable Virtual Memory.
Proceedings of the 19th IEEE International Symposium on Real-Time Distributed Computing, 2016

Efficient Worst-Case Execution Time Analysis of Dynamic Branch Prediction.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

2015
Off-line mapping of multi-rate dependent task sets to many-core platforms.
Real Time Syst., 2015

T-CREST: Time-predictable multi-core architecture for embedded systems.
J. Syst. Archit., 2015

Persistence-based branch misprediction bounds for WCET analysis.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Time-division multiplexing vs network calculus: a comparison.
Proceedings of the 23rd International Conference on Real Time Networks and Systems, 2015

Fernando: An Educational Ahead-of-Time Bytecode Compiler.
Proceedings of the 13th International Workshop on Java Technologies for Real-time and Embedded Systems, 2015

Safety-Critical Java on a Time-Predictable Processor.
Proceedings of the 13th International Workshop on Java Technologies for Real-time and Embedded Systems, 2015

Message Passing on a Time-predictable Multicore Processor.
Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015

2014
A Time-Predictable Memory Network-on-Chip.
Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis, 2014

A Method Cache for Patmos.
Proceedings of the 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014

2013
Data cache organization for accurate timing analysis.
Real Time Syst., 2013

Design and analysis of a hard real-time garbage collector for a Java chip multi-processor.
Concurr. Comput. Pract. Exp., 2013

Mapping a multi-rate synchronous language to a many-core processor.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Chip-multiprocessor hardware locks for safety-critical Java.
Proceedings of the 11th International Workshop on Java Technologies for Real-time and Embedded Systems, 2013

Explicit precedence constraints in safety-critical Java.
Proceedings of the 11th International Workshop on Java Technologies for Real-time and Embedded Systems, 2013

2012
Worst-case execution time analysis-driven object cache design.
Concurr. Comput. Pract. Exp., 2012

On the scalability of time-predictable chip-multiprocessing.
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems, 2012

2011
A Scipt Language-supported Approach to ARGESIM Benchmark C14 'Supply Chain' in Enterprise Dynamics.
Simul. Notes Eur., 2011

Hard real-time garbage collection for a Java chip multi-processor.
Proceedings of the 9th International Workshop on Java Technologies for Real-time and Embedded Systems, 2011

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach.
Proceedings of the Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011

2010
Nonblocking real-time garbage collection.
ACM Trans. Embed. Comput. Syst., 2010

Worst-case execution time analysis for a Java processor.
Softw. Pract. Exp., 2010

WCET driven design space exploration of an object cache.
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, 2010

Worst-Case Analysis of Heap Allocations.
Proceedings of the Leveraging Applications of Formal Methods, Verification, and Validation, 2010

2009
Towards Time-Predictable Data Caches for Chip-Multiprocessors.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2009

Data caching, garbage collection, and the Java memory model.
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems, 2009

2008
Non-blocking object copy for real-time garbage collection.
Proceedings of the 6th International Workshop on Java Technologies for Real-time and Embedded Systems, 2008

Non-blocking root scanning for real-time garbage collection.
Proceedings of the 6th International Workshop on Java Technologies for Real-time and Embedded Systems, 2008

Decoupled root scanning in multi-processor systems.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
picoJava-II in an FPGA.
Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, 2007

2004
Towards a Rapid Prototyping Framework for Architecture Exploration in Embedded Systems.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004


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