Wolfgang Hokenmaier

According to our database1, Wolfgang Hokenmaier authored at least 4 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2006
2008
2010
2012
2014
2016
2018
2020
2022
2024
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1
2
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator.
CoRR, 2024

2020
Verification and Testing Considerations of an In-Memory AI Chip.
Proceedings of the 29th IEEE North Atlantic Test Workshop, 2020

2018
An analysis of an inexpensive memory test solution.
Proceedings of the 27th IEEE North Atlantic Test Workshop, 2018

2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005


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