Wolfgang Günther

J. Graph Algorithms Appl., 2006

2005

Combining ordered best-first search with branch and bound for exact BDD minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

Some Common Synthesis-Simulation-Mismatches.

[BibT_eX]

Stefan Höreth

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Efficient (Non-)Reachability Analysis of Counterexamples.

[BibT_eX]

Burkhard Stubert

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Orthogonal hypergraph routing for improved visibility.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Minimization of the expected path length in BDDs based on local changes.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An improved branch and bound algorithm for exact BDD minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Recursive bi-partitioning of netlists for large number of partitions.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

Pattern-based verification of connections to intellectual property cores.

[BibT_eX]

[DOI]

Integr., 2003

Cross Reduction for Orthogonal Circuit Visualization.

[BibT_eX]

Proceedings of the International Conference on VLSI, 2003

The Case for 2-POF.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Combination of Lower Bounds in Exact BDD Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.

[BibT_eX]

[DOI]

Mitchell A. Thornton

VLSI Design, 2002

Minimization of free BDDs.

[BibT_eX]

[DOI]

Integr., 2002

Minimization of Word-Level Decision Diagrams.

[BibT_eX]

[DOI]

Stefan Höreth

Integr., 2002

Crossing Reduction by Windows Optimization.

[BibT_eX]

[DOI]

Proceedings of the Graph Drawing, 10th International Symposium, 2002

2001

Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf.

[BibT_eX]

[DOI]

PhD thesis, 2001

Using lower bounds during dynamic BDD minimization.

[BibT_eX]

[DOI]

Fabio Somenzi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

History-based dynamic BDD minimization.

[BibT_eX]

[DOI]

Integr., 2001

Performance Driven Optimization for MUX based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Implementation of Read- k-times BDDs on Top of Standard BDD Packages.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Selection of Efficient Re-Ordering Heuristics for MDD Construction.

[BibT_eX]

[DOI]

Frank Schmiedle

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Level Assignment for Displaying Combinational Logic.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Efficient Pattern-Based Verification of Connections to IP Cores .

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Application of linearly transformed BDDs in sequential verification.

[BibT_eX]

[DOI]

Andreas Hett

Proceedings of ASP-DAC 2001, 2001

2000

Fast exact minimization of BDD's.

[BibT_eX]

[DOI]

Nicole Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2000

On the computational power of linearly transformed BDDs.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2000

A Method for Approximate Equivalence Checking.

[BibT_eX]

[DOI]

Mitchell A. Thornton

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Dynamic Re-Encoding During MDD Minimization.

[BibT_eX]

[DOI]

Frank Schmiedle

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Lower Bound Sifting for MDDs.

[BibT_eX]

[DOI]

Dragan Jankovic

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Optimization of sequential verification by history-based dynamic minimization of BDDs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation.

[BibT_eX]

[DOI]

Stefan Höreth

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Improving EAs for Sequencing Problems.

[BibT_eX]

Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints.

[BibT_eX]

Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

<i>k</i>-Layer Straightline Crossing Minimization by Speeding Up Sifting.

[BibT_eX]

[DOI]

Proceedings of the Graph Drawing, 8th International Symposium, 2000

Verification of Designs Containing Black Boxes.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Testability of Circuits Derived from Lattice Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999

Creating hard problem instances in logic synthesis using exact minimization.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Minimization of BDDs using linear transformations based on evolutionary techniques.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

History-Based Dynamic Minimization During BDD Construction.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

Efficient manipulation algorithms for linearly transformed BDDs.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Efficient Graph Coloring by Evolutionary Algorithms.

[BibT_eX]

[DOI]

Nicole Drechsler

Proceedings of the Computational Intelligence, 1999

Generation of Optimal Universal Logic Modules.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Using Lower Bounds During Dynamic BDD Minimization.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Linear Transformations and Exact Minimization of BDDs.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Fast Exact Minimization of BDDs.

[BibT_eX]

[DOI]

Nicole Drechsler