Wing-Kai Chow

According to our database, Wing-Kai Chow authored at least 22 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Pin-Accessible Legalization for Mixed-Cell-Height Circuits.

Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.

Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser

Proceedings of the 2019 International Symposium on Physical Design, 2019

2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.

Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ISPD 2018 Initial Detailed Routing Contest and Benchmarks.

Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu

Proceedings of the 2018 International Symposium on Physical Design, 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.

Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh

Proceedings of the 2018 International Symposium on Physical Design, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.

Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Timing driven routing tree construction.

Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Fence-aware detailed-routability driven placement.

Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

2016

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

IEEE Trans. Very Large Scale Integr. Syst., 2016

Placement: From Wirelength to Detailed Routability.

Wing-Kai Chow, Evangeline F. Y. Young

IPSJ Trans. Syst. LSI Des. Methodol., 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.

Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Legalization algorithm for multiple-row height standard cell design.

Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A robust approach for process variation aware mask optimization.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.

Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham

Integr., 2014

Cell density-driven detailed placement with displacement constraint.

Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young

Proceedings of the International Symposium on Physical Design, 2014

Triple patterning lithography aware optimization for standard cell based design.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

SRP: simultaneous routing and placement for congestion refinement.

Xu He, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the International Symposium on Physical Design, 2013

Ripple 2.0: high quality routability-driven placement via global router integration.

Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Fast Power- and Slew-Aware Gated Clock Tree Synthesis.

Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham

IEEE Trans. Very Large Scale Integr. Syst., 2012

A new clock network synthesizer for modern VLSI designs.

Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham

Integr., 2012

2010

Clock Network Synthesis with Concurrent Gate Insertion.

Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

A dual-MST approach for clock network synthesis.

Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010