Win Chaivipas

According to our database, Win Chaivipas authored at least 13 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS.

Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c.

Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa

IEEE J. Solid State Circuits, 2011

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications.

Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits, 2011

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c.

Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique.

Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2008

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers.

Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2008

Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators.

Win Chaivipas, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2008

2007

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter.

Philipus Chandra Oh, Akira Matsuzawa, Win Chaivipas

IEICE Trans. Electron., 2007

Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop.

Win Chaivipas, Akira Matsuzawa

IEICE Trans. Electron., 2007

2006

Feedforward compensation technique for all digital phase locked loop based synthesizers.

Win Chaivipas, Akira Matsuzawa, Philipus Chandra Oh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006