William J. Song
Orcid: 0000-0001-9170-5986
According to our database1,
William J. Song
authored at least 29 papers
between 2009 and 2024.
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Bibliography
2024
Genie Cache: Non-Blocking Miss Handling and Replacement in Page-Table-Based DRAM Cache.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Parallel Distributed Syst., August, 2023
IEEE Trans. Parallel Distributed Syst., May, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2021
IEEE Trans. Computers, 2021
2020
Energy-Efficient Acceleration of Deep Neural Networks on Realtime-Constrained Embedded Edge Devices.
IEEE Access, 2020
Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2018
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks.
CoRR, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
2016
Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures.
PhD thesis, 2016
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2015
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors.
IEEE Comput. Archit. Lett., 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Temperature regulation in multicore processors using adjustable-gain integral controllers.
Proceedings of the 2015 IEEE Conference on Control Applications, 2015
2014
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2014
ACM Trans. Design Autom. Electr. Syst., 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
2013
Enhancements to FPMIPv6 for improved seamless vertical handover between LTE and heterogeneous access networks.
IEEE Wirel. Commun., 2013
2012
SST: A Scalable Parallel Framework for Architecture-Level Performance, Power, Area and Thermal Simulation.
Comput. J., 2012
Instruction-based energy estimation methodology for asymmetric manycore processor simulations.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012
Proceedings of the 51th IEEE Conference on Decision and Control, 2012
Proceedings of the American Control Conference, 2012
2011
A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration.
SIGMETRICS Perform. Evaluation Rev., 2011
2009
Improvements to seamless vertical handover between mobile WiMAX and 3GPP UTRAN through the evolved packet core.
IEEE Commun. Mag., 2009