William J. Dally

According to our database, William J. Dally authored at least 264 papers between 1985 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.

Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

IEEE J. Solid State Circuits, April, 2024

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.

Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A Novel High-Efficiency Three-Phase Multilevel PV Inverter With Reduced DC-Link Capacitance.

Tuofei Chen, Lei Gu, William J. Dally, Juan Rivas-Davila, John D. Fox

IEEE Trans. Ind. Electron., 2023

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.

Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

IEEE J. Solid State Circuits, 2023

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm.

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany

IEEE J. Solid State Circuits, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren

CoRR, 2023

Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally

CoRR, 2023

SatIn: Hardware for Boolean Satisfiability Inference.

Chenzhuo Zhu, Alexander C. Rucker, Yawen Wang, William J. Dally

CoRR, 2023

Hardware for Deep Learning.

Bill Dally

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture.

Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-Mei W. Hwu

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture.

Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelago, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-mei W. Hwu

Dataset, October, 2022

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update.

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar

IEEE Trans. Computers, 2022

BaM: A Case for Enabling Fine-grain High Throughput GPU-Orchestrated Access to Storage.

Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-Mei W. Hwu

CoRR, 2022

On the model of computation: point.

William J. Dally

Commun. ACM, 2022

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Frontier vs the Exascale Report: Why so long? and Are We Really There Yet?

Peter M. Kogge, William J. Dally

Proceedings of the IEEE/ACM International Workshop on Performance Modeling, 2022

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training.

Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany

Proceedings of the International Conference on Machine Learning, 2022

2021

OP-VENT: A Low-Cost, Easily Assembled, Open-Source Medical Ventilator.

William J. Dally

GetMobile Mob. Comput. Commun., 2021

Evolution of the Graphics Processing Unit (GPU).

William J. Dally, Stephen W. Keckler, David Blair Kirk

IEEE Micro, 2021

Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update.

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar

CoRR, 2021

PatchNet - Short-range Template Matching for Efficient Video Processing.

Huizi Mao, Sibo Zhu, Song Han, William J. Dally

CoRR, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.

Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany

CoRR, 2021

Simba: scaling deep-learning inference with chiplet-based architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Commun. ACM, 2021

SPAA'21 Panel Paper: Architecture-Friendly Algorithms versus Algorithm-Friendly Architectures.

Guy E. Blelloch, William J. Dally, Margaret Martonosi, Uzi Vishkin, Katherine A. Yelick

Proceedings of the SPAA '21: 33rd ACM Symposium on Parallelism in Algorithms and Architectures, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.

Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany

Proceedings of the Fourth Conference on Machine Learning and Systems, 2021

2020

Energy Efficient On-Demand Dynamic Branch Prediction Models.

Milad Mohammadi, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally

IEEE Trans. Computers, 2020

Accelerating Chip Design With Machine Learning.

Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally

IEEE Micro, 2020

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

IEEE J. Solid State Circuits, 2020

Domain-specific hardware accelerators.

William J. Dally, Yatish Turakhia, Song Han

Commun. ACM, 2020

SpArch: Efficient Architecture for Sparse Matrix Multiplication.

Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Optimal Operation of a Plug-in Hybrid Vehicle with Battery Thermal and Degradation Model.

Jongho Kim, Youngsuk Park, John D. Fox, Stephen P. Boyd, William J. Dally

Proceedings of the 2020 American Control Conference, 2020

2019

Darwin: A Genomics Coprocessor.

Yatish Turakhia, Gill Bejerano, William J. Dally

IEEE Micro, 2019

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.

John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

IEEE J. Solid State Circuits, 2019

SysML: The New Frontier of Machine Learning Systems.

Alexander Ratner, Dan Alistarh, Gustavo Alonso, David G. Andersen, Peter Bailis, Sarah Bird, Nicholas Carlini, Bryan Catanzaro, Eric S. Chung, Bill Dally, Jeff Dean, Inderjit S. Dhillon, Alexandros G. Dimakis, Pradeep Dubey, Charles Elkan, Grigori Fursin, Gregory R. Ganger, Lise Getoor, Phillip B. Gibbons, Garth A. Gibson, Joseph E. Gonzalez, Justin Gottschlich, Song Han, Kim M. Hazelwood, Furong Huang, Martin Jaggi, Kevin G. Jamieson, Michael I. Jordan, Gauri Joshi, Rania Khalaf, Jason Knight, Jakub Konecný, Tim Kraska, Arun Kumar, Anastasios Kyrillidis, Jing Li, Samuel Madden, H. Brendan McMahan, Erik Meijer, Ioannis Mitliagkas, Rajat Monga, Derek Gordon Murray, Dimitris S. Papailiopoulos, Gennady Pekhimenko, Theodoros Rekatsinas, Afshin Rostamizadeh, Christopher Ré, Christopher De Sa, Hanie Sedghi, Siddhartha Sen, Virginia Smith, Alex Smola, Dawn Song, Evan Randall Sparks, Ion Stoica, Vivienne Sze, Madeleine Udell, Joaquin Vanschoren, Shivaram Venkataraman, Rashmi Vinayak, Markus Weimer, Andrew Gordon Wilson, Eric P. Xing, Matei Zaharia, Ce Zhang, Ameet Talwalkar

CoRR, 2019

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

CaTDet: Cascaded Tracked Detector for Efficient Object Detection from Video.

Huizi Mao, Taeyoung Kong, Bill Dally

Proceedings of the Second Conference on Machine Learning and Systems, SysML 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Delay Metric for Video Object Detection: What Average Precision Fails to Tell.

Huizi Mao, Xiaodong Yang, Bill Dally

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.

Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany

Proceedings of the International Conference on Computer-Aided Design, 2019

Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup.

Yatish Turakhia, Sneha D. Goenka, Gill Bejerano, William J. Dally

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.

Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.

Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.

Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.

Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018

Optimal Operation of a Plug-In Hybrid Vehicle.

Jason A. Platt, Nicholas Moehle, John D. Fox, William J. Dally

IEEE Trans. Veh. Technol., 2018

Hardware-Enabled Artificial Intelligence.

William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.

John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Efficient Sparse-Winograd Convolutional Neural Networks.

Xingyu Liu, Jeff Pool, Song Han, William J. Dally

Proceedings of the 6th International Conference on Learning Representations, 2018

Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training.

Yujun Lin, Song Han, Huizi Mao, Yu Wang, Bill Dally

Proceedings of the 6th International Conference on Learning Representations, 2018

Bandwidth-efficient deep learning.

Song Han, William J. Dally

Proceedings of the 55th Annual Design Automation Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.

Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly.

Yatish Turakhia, Gill Bejerano, William J. Dally

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance.

Milad Mohammadi, Tor M. Aamodt, William J. Dally

ACM Trans. Archit. Code Optim., 2017

FPGAs versus GPUs in Data centers.

Babak Falsafi, Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, Resit Sendag

IEEE Micro, 2017

HoLiSwap: Reducing Wire Energy in L1 Caches.

Yatish Turakhia, Subhasis Das, Tor M. Aamodt, William J. Dally

CoRR, 2017

Deep Generative Adversarial Networks for Compressed Sensing Automates MRI.

Morteza Mardani, Enhao Gong, Joseph Y. Cheng, Shreyas Vasanawala, Greg Zaharchuk, Marcus T. Alley, Neil Thakur, Song Han, William J. Dally, John M. Pauly, Lei Xing

CoRR, 2017

Exploring the Regularity of Sparse Structure in Convolutional Neural Networks.

Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally

CoRR, 2017

Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.

Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.

Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Efficient methods and hardware for deep learning.

Bill Dally

Proceedings of the Workshop on Trends in Machine-Learning (and impact on computer architecture), 2017

Trained Ternary Quantization.

Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally

Proceedings of the 5th International Conference on Learning Representations, 2017

Efficient Sparse-Winograd Convolutional Neural Networks.

Xingyu Liu, Song Han, Huizi Mao, William J. Dally

Proceedings of the 5th International Conference on Learning Representations, 2017

DSD: Dense-Sparse-Dense Training for Deep Neural Networks.

Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Enhao Gong, Shijian Tang, Erich Elsen, Peter Vajda, Manohar Paluri, John Tran, Bryan Catanzaro, William J. Dally

Proceedings of the 5th International Conference on Learning Representations, 2017

Architecting an Energy-Efficient DRAM System for GPUs.

Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA.

Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William (Bill) J. Dally

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Exploring the Granularity of Sparsity in Convolutional Neural Networks.

Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally

Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017

2016

Reuse Distance-Based Probabilistic Cache Replacement.

Subhasis Das, Tor M. Aamodt, William J. Dally

ACM Trans. Archit. Code Optim., 2016

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.

Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray

IEEE J. Solid State Circuits, 2016

CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution.

Milad Mohammadi, Tor M. Aamodt, William J. Dally

CoRR, 2016

SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <1MB model size.

Forrest N. Iandola, Matthew W. Moskewicz, Khalid Ashraf, Song Han, William J. Dally, Kurt Keutzer

CoRR, 2016

DSD: Regularizing Deep Neural Networks with Dense-Sparse-Dense Training Flow.

Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Shijian Tang, Erich Elsen, Bryan Catanzaro, John Tran, William J. Dally

CoRR, 2016

Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding.

Song Han, Huizi Mao, William J. Dally

Proceedings of the 4th International Conference on Learning Representations, 2016

ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA.

Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William J. Dally

CoRR, 2016

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.

John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

EIE: Efficient Inference Engine on Compressed Deep Neural Network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Deep compression and EIE: Efficient inference engine on compressed deep neural network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015

On-Chip Active Messages for Speed, Scalability, and Efficiency.

R. Curtis Harting, William J. Dally

IEEE Trans. Parallel Distributed Syst., 2015

Learning both Weights and Connections for Efficient Neural Networks.

Song Han, Jeff Pool, John Tran, William J. Dally

CoRR, 2015

On-Demand Dynamic Branch Prediction.

Milad Mohammadi, Song Han, Tor M. Aamodt, William J. Dally

IEEE Comput. Archit. Lett., 2015

Network endpoint congestion control for fine-grained communication.

Nan Jiang, Larry R. Dennison, William J. Dally

Proceedings of the International Conference for High Performance Computing, 2015

Learning both Weights and Connections for Efficient Neural Network.

Song Han, Jeff Pool, John Tran, William J. Dally

Proceedings of the Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, 2015

SLIP: reducing wire energy in the memory hierarchy.

Subhasis Das, Tor M. Aamodt, William J. Dally

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

Scaling the Power Wall: A Path to Exascale.

Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally

Proceedings of the International Conference for High Performance Computing, 2014

Author retrospective for design tradeoffs for tiled CMP on-chip networks.

William J. Dally, James D. Balfour

Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2013

Elastic Buffer Flow Control for On-Chip Networks.

George Michelogiannakis, William J. Dally

IEEE Trans. Computers, 2013

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.

John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray

IEEE J. Solid State Circuits, 2013

Channel reservation protocol for over-subscribed channels and destinations.

George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally

Proceedings of the International Conference for High Performance Computing, 2013

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications.

John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A detailed and flexible cycle-accurate Network-on-Chip simulator.

Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

21st century digital design tools.

William J. Dally, Chris Malachowsky, Stephen W. Keckler

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors.

Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron

ACM Trans. Comput. Syst., 2012

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.

Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Adaptive Backpressure: Efficient buffer management for on-chip networks.

Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Network congestion avoidance through Speculative Reservation.

Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Evaluating Elastic Buffer and Wormhole Flow Control.

George Michelogiannakis, Daniel Becker, William J. Dally

IEEE Trans. Computers, 2011

GPUs and the Future of Parallel Computing.

Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco

IEEE Micro, 2011

Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks.

George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally

IEEE Comput. Archit. Lett., 2011

A compile-time managed multi-level register file hierarchy.

Mark Gebhart, Stephen W. Keckler, William J. Dally

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Power, programmability, and granularity: The challenges of ExaScale computing.

Bill Dally

Proceedings of the 2011 IEEE International Test Conference, 2011

Energy-efficient mechanisms for managing thread context in throughput processors.

Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Panel Statement.

Yves Robert, William J. Dally, Jack J. Dongarra, Satoshi Matsuoka, Robert Schreiber, Horst D. Simon, Uzi Vishkin

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

The utility of fast active messages on many-core chips: Efficient supercomputing project.

R. Curtis Harting, Vishal Parikh, William J. Dally

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2010

The GPU Computing Era.

John Nickolls, William J. Dally

IEEE Micro, 2010

Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures.

JongSoo Park, William J. Dally

Proceedings of the SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2010

Evaluating Bufferless Flow Control for On-chip Networks.

George Michelogiannakis, Daniel Sánchez, William J. Dally, Christos Kozyrakis

Proceedings of the NOCS 2010, 2010

Moving the needle, computer architecture research in academe and industry.

William J. Dally

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Throughput computing.

William J. Dally

Proceedings of the 24th International Conference on Supercomputing, 2010

Block-Parallel Programming for Real-Time Embedded Applications.

David Black-Schaffer, William J. Dally

Proceedings of the 39th International Conference on Parallel Processing, 2010

Fine-grain dynamic instruction placement for L0 scratch-pad memory.

JongSoo Park, James D. Balfour, William J. Dally

Proceedings of the 2010 International Conference on Compilers, 2010

The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer.

William J. Dally, Stephen G. Tell

Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009

Stream Processors.

Mattan Erez, William J. Dally

Proceedings of the Multicore Processors and Systems, 2009

Cost-Efficient Dragonfly Topology for Large-Scale Systems.

John Kim, William J. Dally, Steve Scott, Dennis Abts

IEEE Micro, 2009

Operand Registers and Explicit Operand Forwarding.

James D. Balfour, R. C. Halting, William J. Dally

IEEE Comput. Archit. Lett., 2009

Router designs for elastic buffer on-chip networks.

George Michelogiannakis, William J. Dally

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Allocator implementations for network-on-chip routers.

Daniel U. Becker, William J. Dally

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Indirect adaptive routing on large scale interconnection networks.

Nan Jiang, John Kim, William J. Dally

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Elastic-buffer flow control for on-chip networks.

George Michelogiannakis, James D. Balfour, William J. Dally

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008

A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing.

Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally

IEEE J. Solid State Circuits, 2008

Efficient Embedded Computing.

William J. Dally, James D. Balfour, David Black-Schaffer, James Chen, R. Curtis Harting, Vishal Parikh, JongSoo Park, David Sheffield

Computer, 2008

Hierarchical Instruction Register Organization.

David Black-Schaffer, James D. Balfour, William J. Dally, Vishal Parikh, JongSoo Park

IEEE Comput. Archit. Lett., 2008

An Energy-Efficient Processor Architecture for Embedded Systems.

James D. Balfour, William J. Dally, David Black-Schaffer, Vishal Parikh, JongSoo Park

IEEE Comput. Archit. Lett., 2008

A portable runtime interface for multi-level memory hierarchies.

Mike Houston, Ji Young Park, Manman Ren, Timothy J. Knight, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Technology-Driven, Highly-Scalable Dragonfly Topology.

John Kim, William J. Dally, Steve Scott, Dennis Abts

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies.

Abhishek Das, William J. Dally

Proceedings of the Euro-Par 2008, 2008

A tuning framework for software-managed memory hierarchies.

Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Research Challenges for On-Chip Interconnection Networks.

John D. Owens, William J. Dally, Ron Ho, Doddaballapur Narasimha-Murthy Jayasimha, Stephen W. Keckler, Li-Shiuan Peh

IEEE Micro, 2007

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS.

John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz

IEEE J. Solid State Circuits, 2007

Flattened Butterfly Topology for On-Chip Networks.

John Kim, James D. Balfour, William J. Dally

IEEE Comput. Archit. Lett., 2007

Compilation for explicitly managed memory hierarchies.

Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan

Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Enabling Technology for On-Chip Interconnection Networks.

William J. Dally

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications.

Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Future of on-chip interconnection architectures.

Shekhar Borkar, William J. Dally

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Flattened butterfly: a cost-efficient topology for high-radix networks.

John Kim, William J. Dally, Dennis Abts

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Executing irregular scientific applications on stream architectures.

Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Tradeoff between data-, instruction-, and thread-level parallelism in stream processors.

Jung Ho Ahn, Mattan Erez, William J. Dally

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Interconnect-Centric Computing.

William J. Dally

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Register pointer architecture for efficient embedded processors.

JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Architectural Support for the Stream Execution Model on General-Purpose Processors.

Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy.

Abhishek Das, William J. Dally

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Topology optimization of interconnection networks.

Amit K. Gupta, William J. Dally

IEEE Comput. Archit. Lett., 2006

Data parallel address architecture.

Jung Ho Ahn, William J. Dally

IEEE Comput. Archit. Lett., 2006

Multi-core issues - Multi-Core for HPC: breakthrough or breakdown?

Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Peter H. Beckman

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Interconnect routing and scheduling - Adaptive routing in high-radix clos network.

John Kim, William J. Dally, Dennis Abts

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Sequoia: programming the memory hierarchy.

Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Architecture - The design space of data-parallel memory systems.

Jung Ho Ahn, Mattan Erez, William J. Dally

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

The BlackWidow High-Radix Clos Network.

Steve Scott, Dennis Abts, John Kim, William J. Dally

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Design tradeoffs for tiled CMP on-chip networks.

James D. Balfour, William J. Dally

Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Computer Architecture in the Many-Core Era.

William J. Dally

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI.

Andrew W. Howard, Gu-Yeon Wei, William J. Dally, Paul Horowitz

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Compiling for stream processing.

Abhishek Das, William J. Dally, Peter R. Mattson

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Hot Chips 16: Power, Parallelism, and Memory Performance.

William J. Dally, Keith Diefendorff

IEEE Micro, 2005

A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer.

Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, Mark A. Horowitz

IEEE J. Solid State Circuits, 2005

Fault Tolerance Techniques for the Merrimac Streaming Supercomputer.

Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally

Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Microarchitecture of a High-Radix Router.

John Kim, William J. Dally, Brian Towles, Amit K. Gupta

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Scatter-Add in Data Parallel Architectures.

Jung Ho Ahn, Mattan Erez, William J. Dally

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Explaining the gap between ASIC and custom power: a custom perspective.

Andrew Chang, William J. Dally

Proceedings of the 42nd Design Automation Conference, 2005

2004

Stream Processors: Progammability and Efficiency.

William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das

ACM Queue, 2004

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng

IEEE J. Solid State Circuits, 2004

Globally Adaptive Load-Balanced Routing on Tori.

Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta

IEEE Comput. Archit. Lett., 2004

Buffer and Delay Bounds in High Radix Interconnection Networks.

Arjun Singh, William J. Dally

IEEE Comput. Archit. Lett., 2004

The case for broader computer architecture education: keynote address.

William J. Dally

Proceedings of the 2004 workshop on Computer architecture education, 2004

Adaptive channel queue routing on k-ary n-cubes.

Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles

Proceedings of the SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2004

Analysis and Performance Results of a Molecular Modeling Application on Merrimac.

Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve

Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 2004

Evaluating the Imagine Stream Architecture.

Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Stream Register Files with Indexed Access.

Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003

Guaranteed scheduling for switches with configuration overhead.

Brian Towles, William J. Dally

IEEE/ACM Trans. Netw., 2003

A second-order semidigital clock recovery circuit based on injection locking.

Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

Jitter transfer characteristics of delay-locked loops - theories and design techniques.

Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

Programmable Stream Processors.

Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens

Computer, 2003

Throughput-centric routing algorithm design.

Brian Towles, William J. Dally, Stephen P. Boyd

Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

Merrimac: Supercomputing with Streams.

William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi

Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 2003

GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks.

Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

CMOS High-Speed I/Os - Present and Future.

Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Exploring the VLSI Scalability of Stream Processors.

Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.

Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton

IEEE J. Solid State Circuits, 2002

Worst-case Traffic for Oblivious Routing Functions.

Brian Towles, William J. Dally

IEEE Comput. Archit. Lett., 2002

Migration in Single Chip Multiprocessors.

Kelly A. Shaw, William J. Dally

IEEE Comput. Archit. Lett., 2002

Locality-preserving randomized oblivious routing on torus networks.

Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta

Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002

A Stream Processor Development Platform.

Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Media Processing Applications on the Imagine Stream Processor.

John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

VLSI Design and Verification of the Imagine Processor.

Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

The Imagine Stream Processor.

Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Scalable Opto-Electronic Network (SOENet).

Amit K. Gupta, William J. Dally, Arjun Singh, Brian Towles

Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

Comparing Reyes and OpenGL on a Stream Architecture.

John D. Owens, Brucek Khailany, Brian Towles, William J. Dally

Proceedings of the 2002 ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware, 2002

2001

A Delay Model for Router Microarchitectures.

Li-Shiuan Peh, William J. Dally

IEEE Micro, 2001

Imagine: Media Processing with Streams.

Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner

IEEE Micro, 2001

Guest Editors' Introduction: Hot Chips 12.

William J. Dally, Marc Tremblay, Allen J. Baum

IEEE Micro, 2001

Monolithic chaotic communications system.

Patrick Chiang, William J. Dally, Ming-Ju Edward Lee

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A Delay Model and Speculative Architecture for Pipelined Routers.

Li-Shiuan Peh, William J. Dally

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Route Packets, Not Wires: On-Chip Interconnection Networks.

William J. Dally, Brian Towles

Proceedings of the 38th Design Automation Conference, 2001

Digital systems engineering.

William J. Dally, John W. Poulton

Cambridge University Press, ISBN: 978-0-521-59292-5, 2001

2000

Low-power area-efficient high-speed I/O circuit techniques.

Ming-Ju Edward Lee, William J. Dally, Patrick Chiang

IEEE J. Solid State Circuits, 2000

Efficient conditional operations for data-parallel architectures.

Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Processor Mechanisms for Software Shared Memory.

Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang

Proceedings of the High Performance Computing, Third International Symposium, 2000

Memory access scheduling.

Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Smart Memories: a modular reconfigurable architecture.

Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Register Organization for Media Processing.

Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Flit-Reservation Flow Control.

Li-Shiuan Peh, William J. Dally

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Polygon Rendering on a Stream Architecture.

John D. Owens, William J. Dally, Ujval J. Kapasi, Scott Rixner, Peter R. Mattson, Ben Mowery

Proceedings of the 2000 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, 2000

The role of custom design in ASIC Chips.

William J. Dally, Andrew Chang

Proceedings of the 37th Conference on Design Automation, 2000

Communication Scheduling.

Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens

Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999

Concurrent Event Handling through Multithreading.

Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally

IEEE Trans. Computers, 1999

VLSI Architecture: Past, Present, and Future.

William J. Dally, Steve Lacy

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998

The bleeding edge.

Randall Rettberg, William J. Dally, David E. Culler

IEEE Micro, 1998

A tracking clock recovery receiver for 4-Gbps signaling.

John Poulton, William J. Dally, Steve Tell

IEEE Micro, 1998

An Efficient, Protected Message Interface.

Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang

Computer, 1998

Point Sample Rendering.

J. P. Grossman, William J. Dally

Proceedings of the Rendering Techniques '98, Proceedings of the Eurographics Workshop in Vienna, Austria, June 29, 1998

A Bandwidth-efficient Architecture for Media Processing.

Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.

Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Retrospective: the J-machine.

William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Architecture of a Message-Driven Processor.

William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline.

Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Extended Ehemeral Logging: Log Storage Management for Applications with Long Lived Transactions.

John S. Keen, William J. Dally

ACM Trans. Database Syst., 1997

Transmitter equalization for 4-Gbps signaling.

William J. Dally, John W. Poulton

IEEE Micro, 1997

The M-machine multicomputer.

Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee

Int. J. Parallel Program., 1997

1995

Thread prioritization: A thread scheduling mechanism for multiple-context parallel processors.

Stuart Fiske, William J. Dally

Future Gener. Comput. Syst., 1995

Evaluating the Locality Benefits of Active Messages.

Ellen Spertus, William J. Dally

Proceedings of the Fifth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1995

The Named-State Register File: Implementation and Performance.

Peter R. Nuth, William J. Dally

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Low-latency plesiochronous data retiming.

Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

Architectural and implementation issues for multithreading (panel session I).

Robert A. Iannucci, Anant Agarwal, Bill Dally, Anoop Gupta, Greg Papadopoulos, Burton J. Smith

SIGARCH Comput. Archit. News, 1994

The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers.

William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos

Proceedings of the Parallel Computer Routing and Communication, 1994

Architecture and implementation of the reliable router.

William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos

Proceedings of the Hot Interconnects II, 1994

XEL: Extended Ephemeral Logging for Log Storage Management.

John S. Keen, William J. Dally

Proceedings of the Third International Conference on Information and Knowledge Management (CIKM'94), Gaithersburg, Maryland, USA, November 29, 1994

Hardware Support for Fast Capability-based Addressing.

Nicholas P. Carter, Stephen W. Keckler, William J. Dally

Proceedings of the ASPLOS-VI Proceedings, 1994

Named State and Efficient Context Switching.

Peter R. Nuth, William J. Dally

Proceedings of the Multithreaded Computer Architecture, 1994

Subspace Optimizations.

Kathleen Knobe, William J. Dally

Proceedings of the Automatic Parallelization: New Approaches to Code Generation, 1994

Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement).

William J. Dally

Proceedings of the Multithreaded Computer Architecture, 1994

1993

Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels.

William J. Dally, Hiromichi Aoki

IEEE Trans. Parallel Distributed Syst., 1993

A Universal Parallel Computer Architecture.

William J. Dally

New Gener. Comput., 1993

Performance Evaluation of Ephemeral Logging.

John S. Keen, William J. Dally

Proceedings of the 1993 ACM SIGMOD International Conference on Management of Data, 1993

Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5.

Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

The J-Machine Multicomputer: An Architectural Evaluation.

Michael D. Noakes, Deborah A. Wallach, William J. Dally

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1992

Virtual-Channel Flow Control.

William J. Dally

IEEE Trans. Parallel Distributed Syst., 1992

A Fast Translation Method for Paging on top of Segmentation.

William J. Dally

IEEE Trans. Computers, 1992

The message-driven processor: a multicomputer processing node with efficient mechanisms.

William J. Dally, Stuart Fiske, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Roy E. Davison, Gregory A. Fyler

IEEE Micro, 1992

Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism.

Stephen W. Keckler, William J. Dally

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

The J-Machine Network.

Peter R. Nuth, William J. Dally

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

MDP Design Tools and Methods.

Richard A. Lethin, William J. Dally

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

The Message Driven Processor: An Integrated Multicomputer Processing Element.

William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks.

William J. Dally

IEEE Trans. Computers, 1991

Experiences Implementing Dataflow on a General-Purpose Parallel Computer.

Ellen Spertus, William J. Dally

Proceedings of the International Conference on Parallel Processing, 1991

A Mechanism for Efficient Context Switching.

Peter R. Nuth, William J. Dally

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

A hardware logic simulation system.

Prathima Agrawal, William J. Dally

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Performance Analysis of k-Ary n-Cube Interconnection Networks.

William J. Dally

IEEE Trans. Computers, 1990

Concurrent Aggregates (CA).

Andrew A. Chien, William J. Dally

Proceedings of the Second ACM SIGPLAN Symposium on Princiles & Practice of Parallel Programming (PPOPP), 1990

Simultaneous bidirectional signalling for IC systems.

Kevin Lam, Larry R. Dennison, William J. Dally

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

Experience with CST: Programming and Implementation.

Waldemar Horwat, Andrew A. Chien, William J. Dally

Proceedings of the ACM SIGPLAN'89 Conference on Programming Language Design and Implementation (PLDI), 1989

Universal Mechanisms for Concurrency.

William J. Dally, D. Scott Wills

Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

The J-Machine: A Fine-Gain Concurrent Computer.

William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

Algorithms for Accuracy Enhancement in a Hardware Logic Simulator.

Prathima Agrawal, Raffi Tutundjian, William J. Dally

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Micro-Optimization of Floating Point Operations.

William J. Dally

Proceedings of the ASPLOS-III Proceedings, 1989

1988

Object-oriented concurrent programming in CST.

William J. Dally, Andrew A. Chien

Proceedings of the 1988 ACM SIGPLAN Workshop on Object-based Concurrent Programming, 1988

The Reconfigurable Arithmetic Processor.

Stuart Fiske, William J. Dally

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Mechanisms for Concurrent Computing.

William J. Dally

Proceedings of the International Conference on Fifth Generation Computer Systems, 1988

Finite-grain message passing concurrent computers.

William J. Dally

Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988

1987

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks.

William J. Dally, Charles L. Seitz

IEEE Trans. Computers, 1987

MARS: A Multiprocessor-Based Programmable Accelerator.

Prathima Agrawal, William J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, Raffi Tutundjian

IEEE Des. Test, 1987

Architecture and Design of the MARS Hardware Accelerator.

Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

A VLSI Architecture for Concurrent Data Structures.

William J. Dally

PhD thesis, 1986

The Torus Routing Chip.

William J. Dally, Charles L. Seitz

Distributed Comput., 1986

1985

A Hardware Architecture for Switch-Level Simulation.

William J. Dally, Randal E. Bryant

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

An Object Oriented Architecture.

William J. Dally, James T. Kajiya

Proceedings of the 12th Annual Symposium on Computer Architecture, 1985