William J. Bowhill

According to our database, William J. Bowhill authored at least 13 papers between 1989 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor.

Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2016

The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

IEEE J. Solid State Circuits, 2016

2015

An input pole tuned switching equalization scheme for high-speed serial links.

Sanquan Song, Jian Xu, Fengxiang Cai, Xin Ma, Zibing Yang, Matthew Becker, Larry Tate, Byungsub Kim, Samuel Palermo, William J. Bowhill

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Power management in the Intel Xeon E5 v3.

Ankush Varma, William J. Bowhill, Jason Crop, Corey Gough, Brian Griffith, Dan Kingsley, Krishna Sistla

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2012

A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers.

Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw

IEEE J. Solid State Circuits, 2012

2011

A 32nm 3.1 billion transistor 12-wide-issue Itanium^® processor for mission-critical servers.

Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

1998

High-performance microprocessor design.

Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan, Randy L. Allmon

IEEE J. Solid State Circuits, 1998

A highly testable and diagnosable fabrication process test chip.

Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996

A 433-MHz 64-b quad-issue RISC microprocessor.

Paul E. Gronowski, William J. Bowhill, Dale R. Donchin, Randel P. Blake-Campos, David A. Carlson, Edward R. Equi, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Andy Olesin, Date J. W. Noorlag, Ronald P. Preston

IEEE J. Solid State Circuits, 1996

1995

A 300-MHz 64-b quad-issue CMOS RISC microprocessor.

Bradley J. Benschneider, Andrew J. Black, William J. Bowhill, Sharon M. Britton, Daniel E. Dever, Dale R. Donchin, Robert J. Dupcak, Richard M. Fromm, Mary K. Gowan, Paul E. Gronowski, Michael Kantrowitz, Marc E. Lamere, Shekhar Mehta, Jeanne E. Meyer, Robert O. Mueller, Andy Olesin, Ronald P. Preston, Donald A. Priore, Sribalan Santhanam, Michael J. Smith, Gilbert M. Wolrich

IEEE J. Solid State Circuits, November, 1995

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU

William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf

Digit. Tech. J., 1995

1989

A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor.

Bradley J. Benschneider, William J. Bowhill, Elizabeth M. Copper, Moshe Gavrielov, Paul E. Gronowski, Vijay K. Maheshwari, Victor Peng, Jeffrey D. Pickholtz, Sridhar Samudrala

IEEE J. Solid State Circuits, October, 1989