William Guicquero
Orcid: 0000-0001-8925-0441
According to our database1,
William Guicquero
authored at least 28 papers
between 2013 and 2025.
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Bibliography
2025
IEEE Embed. Syst. Lett., February, 2025
2024
Neural Networks, 2024
A 450µW@50fps Wake-Up Module Featuring Auto-Bracketed 3-Scale Log-Corrected Pattern Recognition and Motion Detection in a 1.5Mpix 8T Global Shutter Imager.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2022
A 1Mb Mixed-Precision Quantized Encoder for Image Classification and Patch-Based Compression.
IEEE Trans. Circuits Syst. Video Technol., 2022
IEEE Trans. Computational Imaging, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
BILLNET: A Binarized Conv3D-LSTM Network with Logic-gated residual architecture for hardware-efficient video inference.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Histogram Compressive Sensing using Shuffled Cellular Automata: the TCSPC sensor use case.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2020
Hardware-Compliant Compressive Image Sensor Architecture Based on Random Modulations and Permutations for Embedded Inference.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Algorithmic Enablers for Compact Neural Network Topology Hardware Design: Review and Trends.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Exploring Hierarchical Machine Learning for Hardware-Limited Multi-Class Inference on Compressed Measurements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
An Analog-to-Information VGA Image Sensor Architecture for Support Vector Machine on Compressive Measurements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Hardware-Friendly Compressive Imaging Based on Random Modulations & Permutations for Image Acquisition and Classification.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Near Sensor Decision Making via Compressed Measurements for Highly Constrained Hardware.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Computational Imaging, 2016
2015
A 3T or 4T pixel compatible DR extension technique suitable for 3D-IC imagers: A 800×512 and 5μm pixel pitch 2D demonstrator.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
On multiple spectral dependent blurring kernels for super-resolution and hyperspectral imaging.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013