William G. Natter
According to our database1,
William G. Natter
authored at least 2 papers
between 2000 and 2001.
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Bibliography
2001
A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000