William Fornaciari

Orcid: 0000-0001-8294-730X

According to our database1, William Fornaciari authored at least 232 papers between 1990 and 2024.

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Bibliography

2024
Enhanced Compiler Technology for Software-based Hardware Fault Detection.
ACM Trans. Design Autom. Electr. Syst., 2024

The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs.
CoRR, 2024

Towards Certifiable Software-Implemented Hardware Fault Tolerance.
Proceedings of the 14th IEEE International Symposium on Industrial Embedded Systems, 2024

VOICE: Value-of-Information for Compute Continuum Ecosystems.
Proceedings of the 27th Conference on Innovation in Clouds, Internet and Networks, 2024


2023
Reliability-oriented resource management for High-Performance Computing.
Sustain. Comput. Informatics Syst., September, 2023

FCPP+Miosix: Scaling Aggregate Programming to Embedded Systems.
IEEE Trans. Parallel Distributed Syst., March, 2023

A Survey on Run-time Power Monitors at the Edge.
ACM Comput. Surv., 2023

Software Fault Tolerance in Real-Time Systems: Identifying the Future Research Questions.
ACM Comput. Surv., 2023

Sema-IIoVT: Emergent Semantic-Based Trustworthy Information-Centric Fog System and Testbed for Intelligent Internet of Vehicles.
IEEE Consumer Electron. Mag., 2023

RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023


Wireless synchronisation as a control problem embedded in new-generation networked automation systems.
Proceedings of the 31st Mediterranean Conference on Control and Automatio, 2023

Efficient control-oriented modelling of heterogeneous large-scale computer cooling systems.
Proceedings of the 31st Mediterranean Conference on Control and Automatio, 2023

Poster Abstract: Run-time Dynamic WCET Estimation.
Proceedings of the 8th ACM/IEEE Conference on Internet of Things Design and Implementation, 2023

Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments.
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE.
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling Challenges.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.
Microprocess. Microsystems, November, 2022

Design of Side-Channel-Resistant Power Monitors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

BarMan: A run-time management framework in the resource continuum.
Sustain. Comput. Informatics Syst., 2022

On the Effectiveness of True Random Number Generators Implemented on FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

The TEXTAROSSA Approach to Thermal Control of Future HPC Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Mixed-Criticality Approach to Fault Tolerance: Integrating Schedulability and Failure Requirements.
Proceedings of the 28th IEEE Real-Time and Embedded Technology and Applications Symposium, 2022

ScaDL 2022 Invited Talk 1: Design of secure power monitors for accelerators, by exploiting ML techniques, in the Euro-HPC TEXTAROSSA project.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

FPGA implementation of BIKE for quantum-resistant TLS.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

On the use of hardware accelerators in QC-MDPC code-based cryptography.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

Feedforward temperature compensation in sub-microsecond wireless clock synchronisation.
Proceedings of the IEEE Conference on Control Technology and Applications, 2022

2021
Scripts for "Work-in-Progress: Run-time pWCET Estimation and Quality Monitoring" RTSS paper.
Dataset, December, 2021

An FPU design template to optimize the accuracy-efficiency-area trade-off.
Sustain. Comput. Informatics Syst., 2021

Automatic identification and hardware implementation of a resource-constrained power model for embedded systems.
Sustain. Comput. Informatics Syst., 2021

Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives.
ACM Comput. Surv., 2021

Work-in-Progress: Run-Time pWCET Estimation and Quality Monitoring.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

A Multi-Level DPM Approach for Real-Time DAG Tasks in Heterogeneous Processors.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls.
Proceedings of the Second Workshop on Next Generation Real-Time Embedded Systems, 2021

Managing the Resource Continuum in a Real Video Surveillance Scenario.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021



2020
WCET benchmarks test on STM32, Raspberry PI/Linux and Raspberry PI/PREEMPT_RT dataset.
Dataset, September, 2020

Dealing with Uncertainty in pWCET Estimations.
ACM Trans. Embed. Comput. Syst., 2020

Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores.
IEEE Trans. Computers, 2020

Probabilistic-WCET reliability: Statistical testing of EVT hypotheses.
Microprocess. Microsystems, 2020

Guest editorial: Special issue on intelligent embedded systems architectures and applications (INTESA).
Microprocess. Microsystems, 2020

The RECIPE approach to challenges in deeply heterogeneous high performance systems.
Microprocess. Microsystems, 2020

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs.
IEEE Embed. Syst. Lett., 2020

TDMH: a communication stack for real-time wireless mesh networks.
CoRR, 2020

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography.
IEEE Access, 2020

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials.
IEEE Access, 2020

Timing Predictability in High-Performance Computing With Probabilistic Real-Time.
IEEE Access, 2020

Tiny Neural Networks for Environmental Predictions: An Integrated Approach with Miosix.
Proceedings of the IEEE International Conference on Smart Computing, 2020

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

A Low Energy FPGA Platform for Real-Time Event-Based Control.
Proceedings of the Workshop on Next Generation Real-Time Embedded Systems, 2020

A Game Theory Approach to Heterogeneous Resource Management: Work-in-Progress.
Proceedings of the 20th International Conference on Embedded Software, 2020

Predictive Resource Management in Energy-constrained Embedded Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Integrating Side Channel Security in the FPGA Hardware Design Flow.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020

2019
Dataset: An Open-hardware Platform for MPSoC Thermal Modeling.
Dataset, July, 2019

Dataset: An Open-hardware Platform for MPSoC Thermal Modeling.
Dataset, May, 2019

The Misconception of Exponential Tail Upper-Bounding in Probabilistic Real Time.
IEEE Embed. Syst. Lett., 2019

The Real-Time Linux Kernel: A Survey on PREEMPT_RT.
ACM Comput. Surv., 2019

An Open-Hardware Platform for MPSoC Thermal Modeling.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Predictive Resource Management for Next-Generation High-Performance Computing Heterogeneous Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Accelerating Automotive Analytics: The M2DC Appliance Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

A Probabilistic Approach to Energy-Constrained Mixed-Criticality Systems.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Run-Time Managed Mobile Application Execution.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019

Why statistical power matters for probabilistic real-time: work-in-progress.
Proceedings of the International Conference on Embedded Software Companion, 2019

Challenges in Deeply Heterogeneous High Performance Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Probabilistic-WCET Reliability: On the experimental validation of EVT hypotheses.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture.
ACM Trans. Design Autom. Electr. Syst., 2018

Event-Based Power/Performance-Aware Thermal Management for High-Density Microprocessors.
IEEE Trans. Control. Syst. Technol., 2018

DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks.
ACM Trans. Archit. Code Optim., 2018

PowerTap: All-digital power meter modeling for run-time power monitoring.
Microprocess. Microsystems, 2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018

chronovise: Measurement-Based Probabilistic Timing Analysis framework.
J. Open Source Softw., 2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

TDMH-MAC: Real-Time and Multi-hop in the Same Wireless MAC.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

Enabling Run-Time Managed Distributed Mobile Computing.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Managing Heterogeneous Resources in HPC Systems.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Back to the future: resource management in post-cloud solutions.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

PowerProbe: Run-time power modeling through automatic RTL instrumentation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A constrained extremum-seeking control for CPU thermal management.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
M2DC - Modular Microserver DataCentre with heterogeneous hardware.
Microprocess. Microsystems, 2017

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
Microprocess. Microsystems, 2017

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers.
J. Parallel Distributed Comput., 2017

Thermal characterization of next-generation workloads on heterogeneous MPSoCs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

DENA: A DVFS-Capable Heterogeneous NoC Architecture.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Just-In-Time Execution Through On-Demand Resource Allocation in HPC Systems.
Proceedings of the International Conference on Algorithms, Computing and Systems, Jeju Island, Republic of Korea, August 10, 2017

Mixed Time-Criticality Process Interferences Characterization on a Multicore Linux System.
Proceedings of the Euromicro Conference on Digital System Design, 2017



2016
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations.
J. Signal Process. Syst., 2016

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs.
IEEE Trans. Parallel Distributed Syst., 2016

Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective.
IET Comput. Digit. Tech., 2016


Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP project.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

The MIG Framework: Enabling Transparent Process Migration in Open MPI.
Proceedings of the 23rd European MPI Users' Group Meeting, EuroMPI 2016, 2016

Runtime resource management for embedded and HPC systems.
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016

Using an adaptive and time predictable runtime system for power-aware HPC-oriented applications.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Demo: A High-Performance, Energy-Efficient Node for a Wide Range of WSN Applications.
Proceedings of the International Conference on Embedded Wireless Systems and Networks, 2016

Event-based control as an enabler for high power density processors.
Proceedings of the Second International Conference on Event-based Control, 2016

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016


V2I Cooperation for Traffic Management with SafeCop.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Resource-Aware Application Execution Exploiting the BarbequeRTRM.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Effective Runtime Resource Management Using Linux Control Groups with the BarbequeRTRM Framework.
ACM Trans. Embed. Comput. Syst., 2015

A control-based methodology for power-performance optimization in NoCs exploiting DVFS.
J. Syst. Archit., 2015

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators.
ACM J. Emerg. Technol. Comput. Syst., 2015

Precision-Aware application execution for Energy-optimization in HPC node system.
CoRR, 2015

Simulation of a runoff model running with multi-criteria in a cluster system.
Proceedings of the Conference on Summer Computer Simulation, 2015

HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

An accurate simulation framework for thermal explorations and optimizations.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015

Flood Prediction Model Simulation With Heterogeneous Trade-Offs In High Performance Computing Framework.
Proceedings of the 29th European Conference on Modelling and Simulation, 2015

Event-based thermal control for high-density processors.
Proceedings of the International Conference on Event-based Control, 2015

TEST: Assessing NoC Policies Facing Aging and Leakage Power.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Harnessing Performance Variability: A HPC-Oriented Application Scenario.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Playful Supervised Smart Spaces (P3S) - A Framework for Designing, Implementing and Deploying Multisensory Play Experiences for Children with Special Needs.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

The MANGO FET-HPC Project: An Overview.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014
An optimal model to partition the evolution of periodic tasks in wireless sensor networks.
Proceedings of the Proceeding of IEEE International Symposium on a World of Wireless, 2014

Combining application adaptivity and system-wide Resource Management on multi-core platforms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Extending a Run-time Resource Management framework to support OpenCL and Heterogeneous Systems.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

Exploiting Performance Counters for Energy Efficient Co-Scheduling of Mixed Workloads on Multi-Core Platforms.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration.
Microprocess. Microsystems, 2013

Optimal hibernation policies for energy efficient stateful operation in high-end wireless sensor nodes.
Proceedings of the IEEE 14th International Symposium on "A World of Wireless, 2013

Power Management Support to Optimal Duty-Cycling in Stateful Multitasking WSN.
Proceedings of the 12th IEEE International Conference on Trust, 2013

An analytical, dynamic, power-performance router model for run-time NoC optimizations.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A bird's eye view on reinforcement learning approaches for power management in WSNs.
Proceedings of the 6th Joint IFIP Wireless and Mobile Networking Conference, 2013

A cycle accurate simulation framework for asynchronous NoC design.
Proceedings of the 2013 International Symposium on System on Chip, 2013

NBTI-aware design of NoC buffers.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A Formal Model for Optimal Autonomous Task Hibernation in Constrained Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Sensor-wise methodology to face NBTI stress of NoC buffers.
Proceedings of the Design, Automation and Test in Europe, 2013

Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Optimal Design of Wireless Sensor Networks.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

A sensor-less NBTI mitigation methodology for NoC architectures.
Proceedings of the IEEE 25th International SOC Conference, 2012

A RTRM proposal for multi/many-core platforms and reconfigurable applications.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Towards energy-efficient functional configuration in WSNs.
Proceedings of the 11th IFAC Conference on Programmable Devices and Embedded Systems, 2012

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Thermal/performance trade-off in network-on-chip architectures.
Proceedings of the 2012 International Symposium on System on Chip, 2012

HANDS: heterogeneous architectures and networks-on-chip design and simulation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Consolidation of multi-tier workloads with performance and reliability constraints.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012


NBTI mitigation in microprocessor designs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Enabling ultra-low power operation in high-end wireless sensor networks nodes.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Software energy optimization through fine-grained function-level voltage and frequency scaling.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Software energy estimation based on statistical characterization of intermediate compilation code.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Estimation of thermal status in multi-core systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Dynamic estimation of thermal status information in embedded MPSoC architectures.
Proceedings of the ARCS 2011, 2011


Run-Time Resource Management at the Operating System level.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

2010



Queueing Network Models for Performance Evaluation of ZigBee-Based WSNs.
Proceedings of the Computer Performance Engineering, 2010

Constrained Power Management: Application to a multimedia mobile platform.
Proceedings of the Design, Automation and Test in Europe, 2010

A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems.
Proceedings of the Architecture of Computing Systems, 2010

CPM: A Cross-Layer Framework to Efficiently Support Distributed Resources Management.
Proceedings of the ARCS '10, 2010

2009
A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Predictive models for multimedia applications power consumption based on use-case and OS level analysis.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Models and Tradeoffs in WSN System-Level Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Measurement, Analysis and Modeling of RTOS System Calls Timing.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC.
IEEE Trans. Computers, 2006

2005
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications.
Proceedings of the 2005 Design, 2005

2004
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.
Proceedings of the Integrated Circuit and System Design, 2004

Analysis and Modeling of Energy Reducing Source Code Transformations.
Proceedings of the 2004 Design, 2004

An area estimation methodology for FPGA based designs at systemc-level.
Proceedings of the 41th Design Automation Conference, 2004

Application-level power management in pervasive computing systems: a case study.
Proceedings of the First Conference on Computing Frontiers, 2004

Source-Level Models for Software Power Optimization.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System.
Proceedings of the Forum on specification and Design Languages, 2003

A First Step Towards Hw/Sw Partitioning of UML Specifications.
Proceedings of the 2003 Design, 2003

Library Functions Timing Characterization for Source-Level Analysis.
Proceedings of the 2003 Design, 2003

Early estimation of the size of VHDL projects.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Static power modeling of 32-bit microprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

The Impact of Source Code Transformations on Software Power and Energy Consumption.
J. Circuits Syst. Comput., 2002

A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems.
Des. Autom. Embed. Syst., 2002

Modeling Assembly Instruction Timing in Superscalar Architectures.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

SIMD Extension to VLIW Multicluster Processors for Embedded Applications.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Metrics for design space exploration of heterogeneous multiprocessor embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

An Agent-Based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems.
Proceedings of the Mobile Agents for Telecommunication Applications, 2001

Dynamic modeling of inter-instruction effects for execution time estimation.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Fast system-level exploration of memory architectures driven by energy-delay metrics.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An Assembly-Level Execution-Time Model for Pipelined Architectures.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A design framework to efficiently explore energy-delay tradeoffs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Development cost and size estimation starting from high-level specifications.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Source-level execution time estimation of C programs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller.
IEEE Des. Test Comput., 2000

A Multi-Level Strategy for Software Power Estimation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Virtualization of FPGA via segmentation (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

An instruction-level functionally-based energy estimation model for 32-bits microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

Power optimization of system-level address buses based on software profiling.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Energy estimation for 32-bit microprocessors.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study.
Proceedings of the IEEE International Conference On Computer Design, 1999

Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems.
Proceedings of the 1999 Design, 1999

A DAG-Based Design Approach for Reconfigurable VLIW Processors.
Proceedings of the 1999 Design, 1999

Power estimation for architectural exploration of HW/SW communication on system-level buses.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

HW/SW Co-design of Embedded Systems.
Proceedings of the Reliable Software Technologies, 1999

1998
Power estimation of embedded systems: a hardware/software codesign approach.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach.
Integr. Comput. Aided Eng., 1998

Concurrent Error Detection at Architectural Level.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Virtual FPGAs: Some Steps Behind the Physical Barriers.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

System-level performance estimation strategy for sw and hw.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

A Model for System-Level Timed Analysis and Profiling.
Proceedings of the 1998 Design, 1998

1997
A VHDL-based approach for power estimation of embedded systems.
J. Syst. Archit., 1997

A Two-Level Cosimulation Environment.
Computer, 1997

Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A Flexible Model for Evaluating the Behavior of Hardware/Software Systems.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Co-synthesis and co-simulation of control-dominated embedded systems.
Des. Autom. Embed. Syst., 1996

The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Partitioning and Exploration Strategies in the TOSCA Co-Design Flow.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
A new architecture for the automatic design of custom digital neural network.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Behavior-driven minimal implementation of digital ANNs.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994
HW/SW Codesign for Embedded Telecom Systems.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

The role of VHDL within the TOSCA hardware/software codesign framework.
Proceedings of the Proceedings EURO-DAC'94, 1994

A methodology for control-dominated systems codesign.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
X-Nets: A visual formalism for system specification and analysis.
Microprocess. Microprogramming, 1993

A spice-based approach to steady state circuit analysis.
Int. J. Circuit Theory Appl., 1993

1990
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description.
Microprocessing and Microprogramming, 1990


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