Werner Geurts
According to our database1,
Werner Geurts
authored at least 15 papers
between 1991 and 2015.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Gener. Comput. Syst., 2015
2013
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR, 2013
2006
Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite.
Proceedings of the International Symposium on System-on-Chip, 2006
2001
ACM Trans. Design Autom. Electr. Syst., 2001
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
1997
Proc. IEEE, 1997
1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1994
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Chess: retargetable code generation for embedded DSP processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994
Loop transformation methodology for fixed-rate video, image and telecom processing applications.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
1992
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
Proceedings of the 29th Design Automation Conference, 1992
1991
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
Proceedings of the VLSI 91, 1991
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
Proceedings of the 28th Design Automation Conference, 1991