Wenyan Lu

Orcid: 0009-0007-1881-962X

According to our database1, Wenyan Lu authored at least 37 papers between 2006 and 2024.

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Bibliography

2024
DPU-Direct: Unleashing Remote Accelerators via Enhanced RDMA for Disaggregated Datacenters.
IEEE Trans. Computers, August, 2024

AMST: Accelerating Large-Scale Graph Minimum Spanning Tree Computation on FPGA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

TianMen: a DPU-based storage network offloading structure for disaggregated datacenters.
Proceedings of the 2024 ACM Symposium on Cloud Computing, 2024

2023
DOE: database offloading engine for accelerating SQL processing.
Distributed Parallel Databases, September, 2023

FlatProxy: A DPU-centric Service Mesh Architecture for Hyperscale Cloud-native Application.
CoRR, 2023

BitColor: Accelerating Large-Scale Graph Coloring on FPGA with Parallel Bit-Wise Engines.
Proceedings of the 52nd International Conference on Parallel Processing, 2023

Exploring the Empowerment of Chinese Women's Discourse in Tik Tok.
Proceedings of the Cross-Cultural Design, 2023

Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Portrait: A holistic computation and bandwidth balanced performance evaluation model for heterogeneous systems.
Sustain. Comput. Informatics Syst., 2022

DOE: Database Offloading Engine for Accelerating SQL Processing.
Proceedings of the 38th IEEE International Conference on Data Engineering Workshops, 2022

2021
ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream Applications.
ACM J. Emerg. Technol. Comput. Syst., 2021

2020
A Quantitative Exploration of Collaborative Pruning and Approximation Computing Towards Energy Efficient Neural Networks.
IEEE Des. Test, 2020

2019
SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks.
ACM Trans. Design Autom. Electr. Syst., 2019

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks.
IEEE Trans. Computers, 2019

MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

TNPU: an efficient accelerator architecture for training convolutional neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability.
J. Low Power Electron., 2018

Joint Design of Training and Hardware Towards Efficient and Accuracy-Scalable Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

AxTrain: Hardware-Oriented Neural Network Training for Approximate Inference.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

CCR: A concise convolution rule for sparse neural network accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Exploiting the Potential of Computation Reuse Through Approximate Computing.
IEEE Trans. Multi Scale Comput. Syst., 2017

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2009
Analysis of channel allocation scheme for wireless cellular networks.
Int. J. Ad Hoc Ubiquitous Comput., 2009

2007
Performance Analysis of IEEE 802.16 Multicast and Broadcast Polling based Bandwidth Request.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

Centralized Scheduling and Channel Assignment in Multi-Channel Single-Transceiver WiMax Mesh Network.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

2006
A Base Station-Coordinated Contention Resolution for IEEE 802.16 PMP Networks.
Proceedings of the Ubiquitous Intelligence and Computing, Third International Conference, 2006

Backtracking Based Handoff Rerouting Algorithm for WiMAX Mesh Mode.
Proceedings of the Ubiquitous Intelligence and Computing, Third International Conference, 2006


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