Wenning Jiang
Orcid: 0000-0002-8585-2813
According to our database1,
Wenning Jiang
authored at least 16 papers
between 2005 and 2024.
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Bibliography
2024
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A TDM-based Analog Front-End for Ear-EEG Recording with 74.5-G Ω Input Impedance, 384-mV DC Tolerance and 0.27-μ Vrms Input-Referred Noise.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024
2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Modified Interleaving Resonant Switched Capacitor Converter with Reduced Output Resistance and In-Situ Startup.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Modified Two-Stage Cascaded Hybrid Converter with Reduced Conduction Loss, Self-Balanced Flying Capacitors and Simplified Interleaving PWM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier.
IEEE J. Solid State Circuits, 2020
2019
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2005
Optimal Position of Isolator to Suppress Double Rayleigh Backscattering Noise in Fiber Raman Amplifiers.
IEICE Trans. Electron., 2005