Wenjuan Lu
Orcid: 0000-0001-6201-8589
According to our database1,
Wenjuan Lu
authored at least 51 papers
between 1999 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024
Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
Design of Human-Machine Compatible Ankle Rehabilitation Robot Based on Equivalent Human Ankle Model.
IEEE Robotics Autom. Lett., February, 2024
A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.
Microelectron. J., February, 2024
Design and Human-Robot Coupling Performance Analysis of Flexible Ankle Rehabilitation Robot.
IEEE Robotics Autom. Lett., January, 2024
Microelectron. J., 2024
Microelectron. J., 2024
Microelectron. J., 2024
Microelectron. J., 2024
A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC.
Microelectron. J., 2024
Towards a New Configurable and Practical Remote Automotive Security Testing Platform.
CoRR, 2024
EVIT-YOLOv8: Construction and research on African Swine Fever facial expression recognition.
Comput. Electron. Agric., 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Work-in-Progress: Towards a New Configurable and Practical Remote Automotive Security Testing Platform.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2024
2023
Scalable Comput. Pract. Exp., November, 2023
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.
Microelectron. J., November, 2023
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
IEEE J. Solid State Circuits, May, 2023
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
Microelectron. J., February, 2023
Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design.
Microelectron. J., February, 2023
Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.
Int. J. Circuit Theory Appl., January, 2023
IEICE Electron. Express, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Performance analysis and trajectory planning of multi-locomotion mode ankle rehabilitation robot.
Robotics Auton. Syst., 2022
An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.
Microelectron. J., 2022
Predicting dose-volume histogram of organ-at-risk using spatial geometric-encoding network for esophageal treatment planning.
J. Ambient Intell. Smart Environ., 2022
Configuration Design and Gait Analysis of Wheel-Legged Mobile Robot Based on the Rubik's Cube Mechanism.
IEEE Access, 2022
Structural Design and Gait Planning of Mobile Robot Based on the Rubik's Cube Mechanism.
Proceedings of the Intelligent Robotics and Applications - 15th International Conference, 2022
Type Synthesis of Six Degrees of Freedom Parallel Mechanism with Decoupled Translation and Rotation.
Proceedings of the Intelligent Robotics and Applications - 15th International Conference, 2022
2021
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.
IEEE J. Solid State Circuits, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEICE Electron. Express, 2020
IEEE Access, 2020
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2016
IEICE Electron. Express, 2016
IEICE Electron. Express, 2016
Power control based time-domain inter-cell interference coordination scheme in DSCNs.
Proceedings of the 2016 IEEE International Conference on Communications, 2016
2015
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier.
Frontiers Inf. Technol. Electron. Eng., 2015
Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102].
IEICE Electron. Express, 2015
A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.
IEICE Electron. Express, 2015
QoE Based Spectrum Allocation Optimization Using Bees Algorithm in Cognitive Radio Networks.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015
2014
Proceedings of the Intelligent Robotics and Applications - 7th International Conference, 2014
2013
Design and analysis of a novel 2-DoF rotational decoupled adjusting parallel mechanism.
Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013
2009
The System Design of Monitoring abnormal Environment Parameter of Vegetable Greenhouse based on Short Message.
Proceedings of the 2009 IEEE/INFORMS International Conference on Service Operations, 2009
2004
Proceedings of the 2004 IEEE Conference on Robotics, Automation and Mechatronics, 2004
1999
Stable Neuro-Adaptive Control for Robots with the Upper Bound Estimation on the Neural Approximation Errors.
J. Intell. Robotic Syst., 1999
Proceedings of the 1999 IEEE International Conference on Robotics and Automation, 1999