Wenjay Hsu

According to our database, Wenjay Hsu authored at least 11 papers between 1988 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2005

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor.

Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena

IEEE J. Solid State Circuits, 2005

2000

A third-generation SPARC V9 64-b microprocessor.

Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You

IEEE J. Solid State Circuits, 2000

1994

Testing of programmable analog neural network chips.

Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu

J. VLSI Signal Process., 1994

1992

Advanced integrated-circuit reliability simulation including dynamic stress effects.

Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda, Chang-Gyu Hwang

IEEE J. Solid State Circuits, March, 1992

1991

Design of reliable VLSI circuits using simulation techniques.

Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda

IEEE J. Solid State Circuits, March, 1991

Testing of Analog Neural Array-Processor Chips.

Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1989

An integrated-circuit reliability simulator-RELY.

Bing J. Sheu, Wen-Jay Hsu, Bang W. Lee

IEEE J. Solid State Circuits, April, 1989

Digital and analog integrated-circuit design with built-in reliability.

Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

An MOS transistor charge model for VLSI design.

Bing J. Sheu, Wen-Jay Hsu, P. K. Ko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988