Weng-Geng Ho
Orcid: 0000-0002-0589-3480
According to our database1,
Weng-Geng Ho
authored at least 31 papers
between 2011 and 2021.
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Bibliography
2021
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications.
Proceedings of the International SoC Design Conference, 2020
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor.
IEEE Trans. Inf. Forensics Secur., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst., 2017
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.
Proceedings of the International Symposium on Integrated Circuits, 2016
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Interceptive side channel attack on AES-128 wireless communications for IoT applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst., 2015
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011