Wenfeng Zhao
Orcid: 0000-0002-2933-750X
According to our database1,
Wenfeng Zhao
authored at least 52 papers
between 2006 and 2024.
Collaborative distances:
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Bibliography
2024
Discov. Internet Things, December, 2024
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet.
IEEE Trans. Biomed. Circuits Syst., February, 2024
AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
Real-Time Segmentation of Unstructured Environments by Combining Domain Generalization and Attention Mechanisms.
Sensors, July, 2023
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V<sub>DD</sub> Assist and Bitline Leakage Compensation.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications.
CoRR, 2023
Proceedings of the Database Systems for Advanced Applications. DASFAA 2023 International Workshops, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Artificial Intelligence Enables Real-Time and Intuitive Control of Prostheses via Nerve Interface.
IEEE Trans. Biomed. Eng., 2022
Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Nonuniform illumination correction for underwater images through a pseudo-siamese network.
Proceedings of the 26th International Conference on Pattern Recognition, 2022
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor.
IEEE Trans. Biomed. Circuits Syst., 2020
In Silico Screening-Based Discovery of Novel Inhibitors of Human Cyclic GMP-AMP Synthase: A Cross-Validation Study of Molecular Docking and Experimental Testing.
J. Chem. Inf. Model., 2020
Discovery of Ubiquitin-Specific Protease 7 (USP7) Inhibitors with Novel Scaffold Structures by Virtual Screening, Molecular Dynamics Simulation, and Biological Evaluation.
J. Chem. Inf. Model., 2020
2019
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Block-Sparse Modeling for Compressed Sensing of Neural Action Potentials and Local Field Potentials.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices.
IEEE Trans. Biomed. Circuits Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Deep Compressive Autoencoder for Action Potential Compression in Large-Scale Neural Recording.
CoRR, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Biomed. Circuits Syst., 2017
BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 4th International Conference on Systems and Informatics, 2017
Proceedings of the 4th International Conference on Systems and Informatics, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm.
IEEE J. Solid State Circuits, 2016
Compressed Sensing for Implantable Neural Recordings Using Co-sparse Analysis Model and Weighted ℓ<sub>1</sub>-Optimization.
CoRR, 2016
Neuronix enables continuous, simultaneous neural recording and electrical microstimulation.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Hardware efficient, deterministic QCAC matrix based compressed sensing encoder architecture for wireless neural recording application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
A programmable fully-integrated microstimulator for neural implants and instrumentation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
Automatic composition of information-providing web services based on query rewriting.
Sci. China Inf. Sci., 2012
A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2008
Proceedings of the 2008 IEEE International Conference on Web Services (ICWS 2008), 2008
2006
Proceedings of the Semantic Web, 2006