Wenbo Liu

According to our database, Wenbo Liu authored at least 8 papers between 2009 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization.

Wenbo Liu, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration.

Wenbo Liu, Pingli Huang, Yun Chiu

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration.

Wenbo Liu, Pingli Huang, Yun Chiu

IEEE J. Solid State Circuits, 2011

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration.

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

IEEE J. Solid State Circuits, 2011

2010

Low-power high-performance SAR ADC design with digital calibration techniques

Wenbo Liu

PhD thesis, 2010

A 12b 22.5/45MS/s 3.0mW 0.059mm² CMOS SAR ADC achieving over 90dB SFDR.

Wenbo Liu, Pingli Huang, Yun Chiu

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization.

Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009