Wen-Hsiang Hu

According to our database1, Wen-Hsiang Hu authored at least 10 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Design and analysis of a mesh-based wireless network-on-chip.
J. Supercomput., 2015

2013
Scalable load balancing congestion-aware Network-on-Chip router architecture.
J. Comput. Syst. Sci., 2013

2012
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms.
Microprocess. Microsystems, 2012

2011
Area and power-efficient innovative congestion-aware Network-on-Chip architecture.
J. Syst. Archit., 2011

A Wireless Network-on-Chip Design for Multicore Platforms.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

2010
Area and Power-efficient Innovative Network-on-Chip Architecurte.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

2009
Parallel FFT Algorithms on Network-on-Chips.
J. Circuits Syst. Comput., 2009

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2006
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2004
A high-performance area-aware DSP processor architecture for video codecs.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004


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