Wen-Hao Liu

According to our database, Wen-Hao Liu authored at least 39 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis.

Rongjian Liang, Chia-Tung Ho, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Challenges for Automating PCB Layout.

Wen-Hao Liu, Anthony Agnesina, Haoxing Mark Ren

Proceedings of the 2024 International Symposium on Physical Design, 2024

GPU/ML-Enhanced Large Scale Global Routing Contest.

Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren

Proceedings of the 2024 International Symposium on Physical Design, 2024

2022

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars.

Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence.

Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition.

Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction.

Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Challenges for Automating Package Routing.

Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification.

Zhen Zhuang, Xing Huang, Genggeng Liu, Wenzhong Guo, Weikang Qian, Wen-Hao Liu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique.

Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes.

Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.

Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser

Proceedings of the 2019 International Symposium on Physical Design, 2019

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew.

Necati Uysal, Wen-Hao Liu, Rickard Ewetz

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ISPD 2018 Initial Detailed Routing Contest and Benchmarks.

Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu

Proceedings of the 2018 International Symposium on Physical Design, 2018

2017

Delay-driven layer assignment for advanced technology nodes.

Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Negotiation-based track assignment considering local nets.

Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition.

Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Skillfully diminishing antenna effect in layer assignment stage.

Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement.

Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu

Proceedings of the International Symposium on Physical Design, 2014

A study on unroutable placement recognition.

Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang

Proceedings of the International Symposium on Physical Design, 2014

A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy.

Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A study on the use of parallel wiring techniques for sub-20nm designs.

Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost.

Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Density-aware Detailed Placement with Instant Legalization.

Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs.

Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing.

Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.

Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li

Proceedings of the International Symposium on Physical Design, 2013

Routing congestion estimation with real design constraints.

Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Optimization of placement solutions for routability.

Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing.

Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li

IEEE Trans. Very Large Scale Integr. Syst., 2012

Optimizing the antenna area and separators in layer assignment of multi-layer global routing.

Wen-Hao Liu, Yih-Lang Li

Proceedings of the International Symposium on Physical Design, 2012

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing.

Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization.

Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

High-quality global routing for multiple dynamic supply voltage designs.

Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Negotiation-based layer assignment for via count and via overflow minimization.

Wen-Hao Liu, Yih-Lang Li

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Multi-threaded collision-aware global routing with bounded-length maze routing.

Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao

Proceedings of the 47th Design Automation Conference, 2010

Minimizing clock latency range in robust clock tree synthesis.

Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.

Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009