Weiwei Shi

Orcid: 0000-0003-4551-8420

Affiliations:
  • Shenzhen University, College of Information Engineering, China
  • Chinese University of Hong Kong, Department of Electronic Engineering, Hong Kong (PhD 2011)


According to our database1, Weiwei Shi authored at least 26 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Area-Delay-Energy-Efficient Approximate Dividers Based on Piecewise Linear Fitting of Surface.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

2023
Cost effective Tanh activation function circuits based on fast piecewise linear logic.
Microelectron. J., 2023

An EEG Signal Processing System Design with Approximate Operations.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
Implementation of SVM-Based Low Power EEG Signal Classification Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2020
Design of basic block of neural signal detection chip.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

Pseudo-NMOS Logic Circuits using ITO-Stabilized ZnO TFTs.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 63.3ps TDC Measurement System Based on FPGA for Pulsed Laser Ranging.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM.
IEEE Access, 2018

Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle Applications.
Proceedings of the 15th International Conference on Synthesis, 2018

2017
Integrating channel selection and feature selection in a real time epileptic seizure detection system.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Subthreshold passive RFID tag's baseband processor core design with custom modules and cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Key component designs of subthreshold baseband processors in passive RF device.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A process-compatible passive RFID tag's digital design for subthreshold operation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2010
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology.
J. Low Power Electron., 2010

2009
A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Design of passive UHF RFID tag in 130nm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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