Weiwei Shan
Orcid: 0000-0001-5520-1326
According to our database1,
Weiwei Shan
authored at least 91 papers
between 2005 and 2024.
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Bibliography
2024
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits.
IEEE J. Solid State Circuits, July, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN.
IEEE J. Solid State Circuits, March, 2024
FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS.
Integr., January, 2024
CoRR, 2024
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
Proceedings of the ACM Turing Award Celebration Conference 2024, 2024
2023
An All-Digital, 1.92-7.32 mV/LSB, 0.5-2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss.
IEEE J. Solid State Circuits, May, 2023
Integr., May, 2023
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.
IEEE J. Solid State Circuits, March, 2023
Sci. China Inf. Sci., February, 2023
A 1.23μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
Microelectron. J., 2023
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Compact and Robust 28nm CMOS Temperature Sensor with Machine Learning Assisted Design for DVFS SoC.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning.
IEEE Trans. Biomed. Circuits Syst., 2022
A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE J. Solid State Circuits, 2021
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
AAD-KWS: a sub-$\mu\mathrm{W}$ keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.
IEEE Trans. Circuits Syst., 2020
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits, 2020
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Using Wind Turbines for Providing Defined Levels of Synthetic Inertia in System Split Scenarios.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2020
Design of Approximate Complex Constant Multiplier for Fast Fourier Transform in 28nm CMOS.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Successive Stripe Artifact Removal Based on Robust PCA for Millimeter Wave Automotive Radar Image.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019
A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures.
J. Circuits Syst. Comput., 2018
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access, 2018
Proceedings of the 17th IEEE International Conference On Trust, 2018
A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS.
Proceedings of the 17th IEEE International Conference On Trust, 2018
Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES.
Proceedings of the 17th IEEE International Conference On Trust, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEICE Electron. Express, 2017
In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications.
IEEE Access, 2017
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2014
IEICE Electron. Express, 2014
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Timing error prediction based adaptive voltage scaling for dynamic variation tolerance.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware.
IEEE Trans. Instrum. Meas., 2013
Int. J. Inf. Commun. Technol., 2013
IEICE Electron. Express, 2013
IEICE Electron. Express, 2013
2012
Proceedings of the Third International Conference on Digital Manufacturing & Automation, 2012
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
2011
A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation.
IEICE Trans. Electron., 2011
2009
J. Circuits Syst. Comput., 2009
Adaptive Fuzzy Logic Controller and Its Application in MEMS Mirror Actuation Feedback Control.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2009
2008
Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
2005
VLSI Implementation of a Self-tuning Fuzzy Controller Based on Variable Universe of Discourse.
Proceedings of the Fuzzy Systems and Knowledge Discovery, Second International Conference, 2005