Weiwei Mao

Orcid: 0009-0007-9149-3881

According to our database1, Weiwei Mao authored at least 21 papers between 1986 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Short-Term Power Load Forecasting Method Based on GRU-Transformer Combined Neural Network Model.
J. Comput. Inf. Technol., 2024

Analysis of the Research Progress of Electromagnetic Railgun Based on CiteSpace.
IEEE Access, 2024

2022
Slicing-Tracking-Detection: Simultaneous Multi-Cylinder Detection From Large-Scale and Complex Point Clouds.
IEEE Trans. Vis. Comput. Graph., 2022

2020
Partial Matching of Large Scale Process Plant Models Using Random Walk on Graphs.
IEEE Access, 2020

2019
SmartWAZ: Design and Implementation of a Smart WiFi Access System Assisted by Zigbee.
IEEE Access, 2019

2013
Quantized-data consensus of second-order multi-agent systems with directed topology.
Proceedings of the 9th Asian Control Conference, 2013

1996
Improving Gate Level Fault Coverage by RTL Fault Grading.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1994
Reducing correlation to improve coverage of delay faults in scan-path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Structure and Metrology for a Single-wire Analog.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1992
IDDQ testing: A review.
J. Electron. Test., 1992

Quietest: A methodology for selecting IDDQ test vectors.
J. Electron. Test., 1992

Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Detection of "Undetectable" Faults Using I<sub>DDQ</sub> Testing.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A quantitative measure of robustness for delay fault testing.
Proceedings of the conference on European design automation, 1992

1991
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage.
Proceedings of the 28th Design Automation Conference, 1991

1990
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Arrangement of latches in scan-path design to improve delay fault coverage.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Variable Observation Time Method for Testing Delay Faults.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
A Simplified Six-waveform Type Method for Delay Fault Testing.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1986
Robust test generation algorithm for stuck-open fault in CMOS circuits.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986


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