Weiqiang Liu

Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ACM Turing Award Celebration Conference 2024, 2024

Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection.

[BibT_eX]

[DOI]

Proceedings of the ACM Turing Award Celebration Conference 2024, 2024

2023

HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.

[BibT_eX]

[DOI]

IEEE Trans. Computers, December, 2023

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Compression-resistant backdoor attack against deep neural networks.

[BibT_eX]

[DOI]

Appl. Intell., September, 2023

Exact and Approximate Squarers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, July, 2023

Detecting backdoor in deep neural networks via intentional adversarial perturbations.

[BibT_eX]

[DOI]

Inf. Sci., July, 2023

ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Dataset authorization control: protect the intellectual property of dataset via reversible feature space adversarial examples.

[BibT_eX]

[DOI]

Appl. Intell., March, 2023

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2023

Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2023

Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

Security and Approximation: Vulnerabilities in Approximation-Aware Testing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2023

Turn Passive to Active: A Survey on Active Intellectual Property Protection of Deep Learning Models.

[BibT_eX]

[DOI]

CoRR, 2023

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Novel Method Against Hardware Trojans in Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Novel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Towards a Lightweight CRYSTALS-Kyber in FPGAs: an Ultra-lightweight BRAM-free NTT Core.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes.

[BibT_eX]

[DOI]

Yuxuan Cui

Chenggang Yan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

An Energy-efficient Approximate DCT Design for Image Processing (Invited).

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

An Efficient Hardware Accelerator of High-Speed NTT for CRYSTALS-Kyber Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A High-Performance SIKE Hardware Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

A Dynamically Configurable PUF and Dynamic Matching Authentication Protocol.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2022

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations.

[BibT_eX]

[DOI]

IEEE Trans. Artif. Intell., 2022

A survey of approximate arithmetic circuits and blocks.

[BibT_eX]

[DOI]

it Inf. Technol., 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2022

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

InFIP: An Explainable DNN Intellectual Property Protection Method based on Intrinsic Features.

[BibT_eX]

[DOI]

CoRR, 2022

Imperceptible and Multi-channel Backdoor Attack against Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

PTB: Robust physical backdoor attacks against deep neural networks in real world.

[BibT_eX]

[DOI]

Comput. Secur., 2022

Active intellectual property protection for deep neural networks through stealthy backdoor and users' identities authentication.

[BibT_eX]

[DOI]

Appl. Intell., 2022

A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A High-Speed CNN Hardware Accelerator with Regular Pruning.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Better Security Estimates for Approximate, IoT-Friendly R-LWE Cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Sample-Specific Backdoor based Active Intellectual Property Protection for Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

Approximate Computing for Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

Security Vulnerabilities and Countermeasures for Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

Approximate Arithmetic Circuits: Design and Applications.

[BibT_eX]

[DOI]

Ke Chen

Proceedings of the Approximate Computing, 2022

2021

AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2021

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering.

[BibT_eX]

[DOI]

Chenggang Yan

Jie Sun

IEEE Trans. Very Large Scale Integr. Syst., 2021

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2021

APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Reduced Precision Redundancy for Reliable Processing of Data.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

BCD Adder Designs Based on Three-Input XOR and Majority Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Stochastic Dividers for Low Latency Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Backdoors hidden in facial features: a novel invisible backdoor attack against face recognition systems.

[BibT_eX]

[DOI]

Peer-to-Peer Netw. Appl., 2021

A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning.

[BibT_eX]

[DOI]

IEEE Open J. Comput. Soc., 2021

A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2021

NaturalAE: Natural and robust physical adversarial examples for object detectors.

[BibT_eX]

[DOI]

J. Inf. Secur. Appl., 2021

SocialGuard: An adversarial example based privacy-preserving technique for social images.

[BibT_eX]

[DOI]

J. Inf. Secur. Appl., 2021

Protect the Intellectual Property of Dataset against Unauthorized Use.

[BibT_eX]

[DOI]

CoRR, 2021

Protecting the Intellectual Properties of Deep Neural Networks with an Additional Class and Steganographic Images.

[BibT_eX]

[DOI]

CoRR, 2021

ActiveGuard: An Active DNN IP Protection Technique via Adversarial Examples.

[BibT_eX]

[DOI]

CoRR, 2021

Robust Backdoor Attacks against Deep Neural Networks in Real Physical World.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Trust, 2021

Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Detect and Remove Watermark in Deep Neural Networks via Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the Information Security - 24th International Conference, 2021

Design of An Approximate FFT Processor Based on Approximate Complex Multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 2-Then-1 Bit/Cycle Asynchronous SAR ADC with Background Offset Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Performance Systolic Array Montgomery Multiplier for SIKE.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (Invited Paper).

[BibT_eX]

[DOI]

Mingfu Xue

Jian Wang

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

GOMIL: Global Optimization of Multiplier by Integer Linear Programming.

[BibT_eX]

[DOI]

Weihua Xiao

Weikang Qian

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance.

[BibT_eX]

[DOI]

Zhe Liu

Kim-Kwang Raymond Choo

Muhammad Khurram Khan

IEEE Trans. Emerg. Top. Comput., 2020

An Efficient and Parallel R-LWE Cryptoprocessor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Hybrid Low Radix Encoding-Based Approximate Booth Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Profile-Based Output Error Compensation for Approximate Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Mathematical Modeling Analysis of Strong Physical Unclonable Functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

High Performance Modular Multiplication for SIDH.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots.

[BibT_eX]

[DOI]

Secur. Commun. Networks, 2020

Approximate Computing: From Circuits to Applications [Scanning the Issue].

[BibT_eX]

[DOI]

Michael J. Schulte

Proc. IEEE, 2020

A Retrospective and Prospective View of Approximate Computing [Point of View}.

[BibT_eX]

[DOI]

Michael Shulte

Proc. IEEE, 2020

Scanning the Issue.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

Ten years of hardware Trojans: a survey from the attacker's perspective.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2020

Design, evaluation and application of approximate-truncated Booth multipliers.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2020

3D Invisible Cloak.

[BibT_eX]

[DOI]

CoRR, 2020

Use the Spear as a Shield: A Novel Adversarial Example based Privacy-Preserving Technique against Membership Inference Attacks.

[BibT_eX]

[DOI]

CoRR, 2020

Robust and Natural Physical Adversarial Examples for Object Detectors.

[BibT_eX]

[DOI]

CoRR, 2020

DNN Intellectual Property Protection: Taxonomy, Methods, Attack Resistance, and Evaluations.

[BibT_eX]

[DOI]

CoRR, 2020

LOPA: A linear offset based poisoning attack method against adaptive fingerprint authentication system.

[BibT_eX]

[DOI]

Comput. Secur., 2020

Machine Learning Security: Threats, Countermeasures, and Evaluations.

[BibT_eX]

[DOI]

IEEE Access, 2020

Active DNN IP Protection: A Novel User Fingerprint Management and DNN Authorization Control Technique.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Trust, 2020

Transformer PUF : A Highly Flexible Configurable RO PUF Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

A Novel Feature Extraction Strategy for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DC-LSTM: Deep Compressed LSTM with Low Bit-Width and Structured Matrices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design and Implementation of an Approximate Softmax Layer for Deep Neural Networks.

[BibT_eX]

[DOI]

Yue Gao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Programmable Ring Oscillator PUF Based on Switch Matrix.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Security Analysis of Hardware Trojans on Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Efficient Hardware Generator for Massive Non-Stationary Fading Channels.

[BibT_eX]

[DOI]

Proceedings of the IEEE Globecom Workshops, 2020

Embedding Backdoors as the Facial Features: Invisible Backdoor Attacks Against Face Recognition Systems.

[BibT_eX]

[DOI]

Proceedings of the ACM TUR-C'20: ACM Turing Celebration Conference, 2020

2019

Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

Tingting Zhang

Vikramkumar Pudi

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Design and Analysis of Approximate Redundant Binary Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2019

High-performance approximate half and full adder cells using NAND logic gate.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Lattice-based Cryptography for IoT in A Quantum World: Are We Ready?

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method.

[BibT_eX]

[DOI]

IEEE Access, 2019

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Theoretical Analysis of Configurable RO PUFs and Strategies to Enhance Security.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Dynamic Reconfigurable PUFs Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

An Improved Automatic Hardware Trojan Generation Platform.

[BibT_eX]

[DOI]

Shichao Yu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Multi-Incentive Delay-Based (MID) PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUF.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018

Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Peipei Yin

J. Signal Process. Syst., 2018

Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders.

[BibT_eX]

[DOI]

Xiao-Ping Cui

Shumin Wang

J. Signal Process. Syst., 2018

Design, Evaluation and Application of Approximate High-Radix Dividers.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

Data Compression Device Based on Modified LZ4 Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2018

Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.

[BibT_eX]

[DOI]

IEEE Access, 2018

A Co-training Based Hardware Trojan Detection Technique by Exploiting Unlabeled ICs and Inaccurate Simulation Models.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference On Trust, 2018

A Probabilistic Error Model and Framework for Approximate Booth Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design of Majority Logic (ML) Based Approximate Full Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Optimization of Modular Multiplication for SIDH.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design of Approximate FFT with Bit-width Selection Algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Application of an Approximate 2-D Convolver with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Modelling Attack Analysis of Configurable Ring Oscillator (CRO) PUF Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Design of Dynamic Range Approximate Logarithmic Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A machine learning attack resistant multi-PUF design on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Approximate Computing and Its Application to Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the Cyber-Physical Systems Security., 2018

2017

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes.

[BibT_eX]

[DOI]

Xiao-Ping Cui

Wenwen Dong

IEEE Trans. Computers, 2017

Design and operational assessment of an intra-cell hybrid L2 cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

XOR gate based low-cost configurable RO PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of Approximate Logarithmic Multipliers.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

DC MUX PUF: A highly reliable feed-back MUX PUF based on measuring duty cycle.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Multiprecision Multiplication on ARMv8.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016

Design and Analysis of Inexact Floating-Point Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

A Modified Partial Product Generator for Redundant Binary Multipliers.

[BibT_eX]

[DOI]

Xiao-Ping Cui

Chen Xin

IEEE Trans. Computers, 2016

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A fully parallel approximate CORDIC design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design of approximate Redundant Binary multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Performance Evaluation of Approximate Floating-Point Multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: An automatic evaluation platform for physical unclonable function test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes.

[BibT_eX]

[DOI]

Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015

Improving RO PUF design using frequency distribution characteristics.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Design of 3-D quantum-dot cellular automata adders.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

RO PUF design in FPGAs with new comparison strategies.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Security Issues in QCA Circuit Design - Power Analysis Attacks.

[BibT_eX]

[DOI]

Saket Srivastava

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

2013

QCA Systolic Array Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Power analysis attack of QCA circuits: A case study of the Serpent cipher.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Cost-efficient decimal adder design in Quantum-dot cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A review of QCA adders and metrics.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

Design rules for Quantum-dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

QCA Systolic Matrix Multiplier.

[BibT_eX]

[DOI]