Weihuang Wang

According to our database, Weihuang Wang authored at least 6 papers between 2007 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.

Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi

J. Low Power Electron., 2009

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.

Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2007

Speculative Energy Scheduling for LDPC Decoding.

Weihuang Wang, Gwan Choi

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.

Kiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An FPGA Implementation of Dirty Paper Precoder.

Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan Choi, Zixiang Xiong, Mark B. Yeary, Alan Harris

Proceedings of IEEE International Conference on Communications, 2007

Minimum-energy LDPC decoder for real-time mobile application.

Weihuang Wang, Gwan Choi

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007