Weiguang Sheng
Orcid: 0000-0002-7831-526X
According to our database1,
Weiguang Sheng
authored at least 41 papers
between 2008 and 2024.
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Bibliography
2024
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
An Efficient near-Bank Processing Architecture for Personalized Recommendation System.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett., 2022
2021
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 7th IEEE International Conference on Big Data Security on Cloud, 2021
2020
IEEE Trans. Parallel Distributed Syst., 2020
Remote. Sens., 2020
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network.
J. Digit. Imaging, 2019
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
2018
Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems.
ACM Trans. Storage, 2018
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems.
Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018
Optimizing the data placement and transformation for multi-bank CGRA computing system.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Microelectron. J., 2016
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
J. Circuits Syst. Comput., 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.
Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics.
Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015
An automatic translation and parallelization system for general purpose reconfigurable processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2009
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.
Proceedings of the 46th Design Automation Conference, 2009
2008
Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008