Weichen Liu

Orcid: 0000-0002-8576-6130

According to our database1, Weichen Liu authored at least 183 papers between 2007 and 2024.

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Bibliography

2024
Domino-Pro-Max: Toward Efficient Network Simplification and Reparameterization for Embedded Hardware Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Introduction to Special Issue on In/Near Memory and Storage Computing for Embedded Systems.
ACM Trans. Embed. Comput. Syst., November, 2024

EvoLP: Self-Evolving Latency Predictor for Model Compression in Real-Time Edge Systems.
IEEE Embed. Syst. Lett., June, 2024

DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip.
ACM Trans. Archit. Code Optim., March, 2024

Automated Optical Accelerator Search Toward Superior Acceleration Efficiency, Inference Robustness, and Development Speed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

The Psychological Mechanism of Moral Leadership Influencing Responsible Subordinate Behavior.
Syst., 2024

Efficient Deep Learning Infrastructures for Embedded Computing Systems: A Comprehensive Survey and Future Envision.
CoRR, 2024

Enabling Energy-Efficient Deployment of Large Language Models on Memristor Crossbar: A Synergy of Large and Small.
CoRR, 2024

Launching Your VR Neuroscience Laboratory.
CoRR, 2024

Virtual Psychedelia.
CoRR, 2024

FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual Inspection.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Double-Win NAS: Towards Deep-to-Shallow Transformable Neural Architecture Search for Intelligent Embedded Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Efficient FPGA-Based Sparse Matrix-Vector Multiplication With Data Reuse-Aware Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

EdgeCompress: Coupling Multidimensional Model Compression and Dynamic Inference for EdgeAI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Automated Optical Accelerator Search: Expediting Green and Ubiquitous DNN-Powered Intelligence.
IEEE Des. Test, December, 2023

On Hardware-Aware Design and Optimization of Edge Intelligence.
IEEE Des. Test, December, 2023

CRIMP: Compact & Reliable DNN Inference on In-Memory Processing via Crossbar-Aligned Compression and Non-ideality Adaptation.
ACM Trans. Embed. Comput. Syst., October, 2023

LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Latency-constrained DNN architecture learning for edge systems using zerorized batch normalization.
Future Gener. Comput. Syst., May, 2023

SurgeNAS: A Comprehensive Surgery on Hardware-Aware Differentiable Neural Architecture Search.
IEEE Trans. Computers, April, 2023

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Efficient Response Time Bound for Typed DAG Tasks.
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023

iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

FIONA: Fine-grained Incoherent Optical DNN Accelerator Search for Superior Efficiency and Robustness.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards Efficient Convolutional Neural Network for Embedded Hardware via Multi-Dimensional Pruning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Human motion trajectory generation based on AWR1642.
Proceedings of the International Conference on Computers, 2023

Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge.
ACM Trans. Embed. Comput. Syst., September, 2022

Solving Dynamic Multiobjective Problem via Autoencoding Evolutionary Search.
IEEE Trans. Cybern., 2022

Locking Protocols for Parallel Real-Time Tasks With Semaphores Under Federated Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CARTAD: Compiler-Assisted Reinforcement Learning for Thermal-Aware Task Scheduling and DVFS on Multicores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fast and Low Overhead Metadata Operations for NVM-Based File System Using Slotted Paging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes.
IEEE Trans. Computers, 2022

Bringing AI to edge: From deep learning's perspective.
Neurocomputing, 2022

EDLAB: A Benchmark for Edge Deep Learning Accelerators.
IEEE Des. Test, 2022

Evolutionary game-based incentive models for sustainable trust enhancement in a blockchained shared manufacturing network.
Adv. Eng. Informatics, 2022

The Virtual-Augmented Reality Simulator: Evaluating OST-HMD AR calibration algorithms in VR.
Proceedings of the 2022 IEEE Conference on Virtual Reality and 3D User Interfaces Abstracts and Workshops, 2022

A DirectX-Based DICOM Viewer for Multi-user Surgical Planning in Augmented Reality.
Proceedings of the Advances in Visual Computing - 17th International Symposium, 2022

Collate: Collaborative Neural Network Learning for Latency-Critical Edge Systems.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded Hardware.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on Hardware-Aware Neural Architecture Search.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
MARCO: A High-performance Task Mapping and Routing Co-optimization Framework for Point-to-Point NoC-based Heterogeneous Computing Systems.
ACM Trans. Embed. Comput. Syst., 2021

Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Priority Assignment on Partitioned Multiprocessor Systems With Shared Resources.
IEEE Trans. Computers, 2021

On the Analysis of Parallel Real-Time Tasks With Spin Locks.
IEEE Trans. Computers, 2021

Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs.
ACM J. Emerg. Technol. Comput. Syst., 2021

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Cryptocurrency Price Prediction Model Based on Twitter Sentiment Indicators.
Proceedings of the Big Data and Security - Third International Conference, 2021

Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Fault-Tolerant Routing Mechanism in 3D Optical Network-on-Chip Based on Node Reuse.
IEEE Trans. Parallel Distributed Syst., 2020

Hardware-Software Collaborative Thermal Sensing in Optical Network-on-Chip-based Manycore Systems.
ACM Trans. Embed. Comput. Syst., 2020

Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Thermal-Aware Design and Simulation Approach for Optical NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Autonomous temperature sensing for optical network-on-chip.
J. Syst. Archit., 2020

Disrupted Rich Club Organization of Hemispheric White Matter Networks in Bipolar Disorder.
Frontiers Neuroinformatics, 2020

Cross-filter compression for CNN inference acceleration.
CoRR, 2020

Evaluation of Low-end Virtual Reality Content of Cultural Heritage: A Preliminary Study with Eye Movement.
Proceedings of the JCDL '20: Proceedings of the ACM/IEEE Joint Conference on Digital Libraries in 2020, 2020

Mitigation of Tampering Attacks for MR-Based Thermal Sensing in Optical NoCs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices.
Proceedings of the 26th IEEE International Conference on Parallel and Distributed Systems, 2020

Person Re-Identification Via Pose-Aware Multi-Semantic Learning.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2020

Occlusion-Aware GAN for Face De-Occlusion in the Wild.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2020

COSMA: An Efficient Concurrency-Oriented Space Management Scheme for In-memory File Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

EdgeNAS: Discovering Efficient Neural Architectures for Edge Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Load-aware Adaptive Cache Management Scheme for Enterprise-level Stackable Cryptographic File System<sup>*</sup>.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

CalAR: A C++ Engine for Augmented Reality Applications on Android Mobile Devices.
Proceedings of the Engineering Reality of Virtual Reality 2020, 2020

LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router Reuse.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Mobi-PMFS: An Efficient and Durable In-Memory File System for Mobile Devices.
Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Contention Minimized Bypassing in SMART NoC.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Towards Fast and Lightweight Checkpointing for Mobile Virtualization Using NVRAM.
IEEE Trans. Parallel Distributed Syst., 2019

Response Time Bounds for Typed DAG Parallel Tasks on Heterogeneous Multi-Cores.
IEEE Trans. Parallel Distributed Syst., 2019

Real-Time Scheduling of DAG Tasks with Arbitrary Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2019

An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit.
ACM Trans. Embed. Comput. Syst., 2019

Timing-Anomaly Free Dynamic Scheduling of Conditional DAG Tasks on Multi-Core Systems.
ACM Trans. Embed. Comput. Syst., 2019

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router.
IEEE Trans. Computers, 2019

NV-eCryptfs: Accelerating Enterprise-Level Cryptographic File System with Non-Volatile Memory.
IEEE Trans. Computers, 2019

CASS: Criticality-Aware Standby-Sparing for real-time systems.
J. Syst. Archit., 2019

Leaking your engine speed by spectrum analysis of real-Time scheduling sequences.
J. Syst. Archit., 2019

Implementation issues in optimization algorithms: do they matter?
J. Exp. Theor. Artif. Intell., 2019

A Branch-and-Bound-Based Crossover Operator for the Traveling Salesman Problem.
Int. J. Cogn. Informatics Nat. Intell., 2019

Energy-efficient crypto acceleration with HW/SW co-design for HTTPS.
Future Gener. Comput. Syst., 2019

Dynamic No-Fly Zone for Drones.
Proceedings of the 2019 IEEE SmartWorld, 2019

Suspension-Based Locking Protocols for Parallel Real-Time Tasks.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

Design of a Hierarchical Clos-Benes Optical Network-on-Chip Architecture.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

WDM-MDM Silicon-Based Optical Switching for Data Center Networks.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

HolyLight: A Nanophotonic Accelerator for Deep Learning in Data Centers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Thermal Sensing Using Micro-ring Resonators in Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Analyzing GEDF Scheduling for Parallel Real-Time Tasks with Arbitrary Deadlines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Scheduling and Analysis of Parallel Real-Time Tasks with Semaphores.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
ConsensUs: Supporting Multi-Criteria Group Decisions by Visualizing Points of Disagreement.
ACM Trans. Soc. Comput., 2018

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

TripImputor: Real-Time Imputing Taxi Trip Purpose Leveraging Multi-Sourced Urban Data.
IEEE Trans. Intell. Transp. Syst., 2018

Analyzing Data Cache Related Preemption Delay With Multiple Preemptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Chip Temperature Optimization for Dark Silicon Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018

Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing.
Secur. Commun. Networks, 2018

CrowdExpress: A Probabilistic Framework for On-Time Crowdsourced Package Deliveries.
CoRR, 2018

ACA-SDS: Adaptive Crypto Acceleration for Secure Data Storage in Big Data.
IEEE Access, 2018

Work-in-Progress: Response Time Bounds for Typed DAG Parallel Tasks on Heterogeneous Multi-cores.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Fine-Grained Task-Level Parallel and Low Power H.264 Decoding in Multi-Core Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

Communication optimization for thermal reliable optical network-on-chip: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era.
IEEE Trans. Parallel Distributed Syst., 2017

Hardware-software collaboration for dark silicon heterogeneous many-core systems.
Future Gener. Comput. Syst., 2017

Revisiting GPC and AND Connector in Real-Time Calculus.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Quantitative Modeling of Thermo-Optic Effects in Optical Networks-on-Chip.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Combining two local searches with crossover: an efficient hybrid algorithm for the traveling salesman problem.
Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Fixed priority scheduling of real-time flows with arbitrary deadlines on smart NoCs: work-in-progress.
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017

Efficient drone hijacking detection using onboard motion sensors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Task Mapping on SMART NoC: Contention Matters, Not the Distance.
Proceedings of the 54th Annual Design Automation Conference, 2017

ConsesnsUs: Visualizing Points of Disagreement for Multi-Criteria Collaborative Decision Making.
Proceedings of the 2017 ACM Conference on Computer Supported Cooperative Work and Social Computing, 2017

Communication optimization for thermal reliable many-core systems: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Technique of Application Mapping and Scheduling on Real-Time Multiprocessor Systems for Throughput Optimization.
ACM Trans. Embed. Comput. Syst., 2016

Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme.
J. Circuits Syst. Comput., 2016

Through Global Sharing to Improve Network Efficiency for Radio-Frequency Interconnect Based Network-on-Chip.
IEEE Access, 2016

Hybridizing Different Local Search Algorithms with Each Other and Evolutionary Computation: Better Performance on the Traveling Salesman Problem.
Proceedings of the Genetic and Evolutionary Computation Conference, 2016

ApproxMap: On task allocation and scheduling for resilient applications.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

<i>n</i>Code: limiting harmful writes to emerging mobile NVRAM through code swapping.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization.
Proceedings of the 2015 International Conference on Compilers, 2015

Hybrid Ejection Chain Methods for the Traveling Salesman Problem.
Proceedings of the Bio-Inspired Computing - Theories and Applications, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014

Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Enhancing lifetime of NVM-based main memory with bit shifting and flipping.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

DR. Swap: energy-efficient paging for smartphones.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Building high-performance smartphones via non-volatile memory: The swap approach.
Proceedings of the 2014 International Conference on Embedded Software, 2014

A systematic network-on-chip traffic modeling and generation methodology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.
IEEE Trans. Parallel Distributed Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012

2011
Power Gating Aware Task Scheduling in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems.
IEEE Trans. Parallel Distributed Syst., 2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
IEEE Embed. Syst. Lett., 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

2009
Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs.
Microprocess. Microsystems, 2009

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow.
IEEE Embed. Syst. Lett., 2009

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A case study of on-chip sensor network in multiprocessor system-on-chip.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization.
Proceedings of the 29th IEEE Real-Time Systems Symposium, 2008

2007
An Efficient Algorithm for Online Soft Real-Time Task Placement on Reconfigurable Hardware Devices.
Proceedings of the Tenth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2007), 2007

Improved Schedulability Analysis of EDF Scheduling on Reconfigurable Hardware Devices.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007


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