Wei Zhao

Orcid: 0000-0003-2765-498X

Affiliations:
  • Huazhong University of Science and Technology, Wuhan National Laboratory for Optoelectronics, China


According to our database1, Wei Zhao authored at least 15 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
CMD: A Cache-assisted GPU Memory Deduplication Architecture.
CoRR, 2024

A Read Latency Variation Aware Independent Read Scheme for QLC SSDs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs.
ACM Trans. Archit. Code Optim., September, 2023

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
ZNSKV: Reducing Data Migration in LSMT-Based KV Stores on ZNS SSDs.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage.
IEEE Trans. Computers, 2021

MORE<sup>2</sup>: Morphable Encryption and Encoding for Secure NVM.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Improving the energy efficiency of STT-MRAM based approximate cache.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Cross-point Resistive Memory: Nonideal Properties and Solutions.
ACM Trans. Design Autom. Electr. Syst., 2019

ReRAM Crossbar-Based Analog Computing Architecture for Naive Bayesian Engine.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2012
vSuit: QoS-oriented Scheduler in Network Virtualization.
Proceedings of the 26th International Conference on Advanced Information Networking and Applications Workshops, 2012


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